Results 171 to 180 of about 10,455 (213)

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

IEEE Transactions on Computers, 2016
This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a ...
Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi   +3 more
openaire   +1 more source

An SEU (Single-event Upset) Mitigation Strategy on Read-Write Separation SRAM Cell for Low Power Consumption

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020
SRAM for space applications continues to be disturbed by highly energetic charged particles along with technology node scaling, that is the single-event upset (SEU) in terms of time perspective. A 14T read-write separation SRAM cell in low power mode is proposed using radiation hardened by design (RHBD) technique, not only robust to SEU but also ...
Ze-Xin Su, Bo Li, Xiao-Hui Su, Fan-Yu Liu, Zheng-Sheng Han, Xin-Yu Liu, Konstantin O. Pctrosyants, Igor A. Kharitonov   +7 more
openaire   +1 more source

Single-Event Upset (SEU) Model Verification and Threshold Determination Using Heavy Ions in a Bipolar Static RAM

IEEE Transactions on Nuclear Science, 1985
Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and 0 ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device.
J. A. Zoutendyk, L. S. Smith, G. A. Soli, P. Thieberger, H. E. Wegner   +4 more
openaire   +1 more source

Notice of Violation of IEEE Publication Principles: Selective Triple Modular Redundancy for Single Event Upset (SEU) Mitigation

2009 NASA/ESA Conference on Adaptive Hardware and Systems, 2009
This paper represents a design technique for hardening circuits mapped onto FPGAs. An effective and simple algorithm for signal probabilities has been used to detect SEU (single event upset) sensitive gates for a given circuit. The circuit can be hardened against radiation effects by applying triple modular redundancy (TMR) technique to only these ...
Xiaoxuan She, P.K. Samudrala
openaire   +1 more source

SEU (Single Event Upset) Vulnerability of the Zilog Z-80 and NSC-800 Microprocessors,

1986
Abstract : A detailed analysis of the SEU vulnerability of the Zilog Z-80 microprocessor is presented based upon data obtained with heavy ions and protons. The analysis demonstrates a method for separating upsets of the general purpose registers from upsets of the internal latches.
J. Cusick, C. King, W. A. Kolasinski, R. Koga   +3 more
openaire   +1 more source

Experimental Determination of Single-Event Upset (SEU) as a Function of Collected Charge in Bipolar Integrated Circuits

IEEE Transactions on Nuclear Science, 1984
Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as
J. A. Zoutendyk, C. J. Malone, L. S. Smith   +2 more
openaire   +1 more source

Neutron Induced Single Event Upset (SEU) Testing of Commercial Memory Devices with Embedded Error Correction Codes (ECC)

2017 IEEE Radiation Effects Data Workshop (REDW), 2017
Results of neutron induced single event upset testing of devices with embedded error correction codes are described. Specifically, Cypress CY7C1061GE30-10BVXI and CY7C1061GE-10BVXI 16-Mbit Static Random Access Memories (SRAMs), and a memory system, consisting of a Tundra Tsi107 PowerPC Host Bridge interfacing with nine Micron MT48LC32M8A2TG-75ITD 256 ...
John M. Bird, Michael K. Peters, Travis Z. Fullem, Michael J. Tostanoski, Terrence F. Deaton, Kristianto Hartojo, Roy E. Strayer   +6 more
openaire   +1 more source

Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2018
This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically.
Zhen Gao, Lina Yan, Jinhua Zhu, Ruishi Han, Pedro Reviriego   +4 more
openaire   +1 more source

Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained from Model Verification

IEEE Transactions on Nuclear Science, 1987
Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator ...
J. A. Zoutendyk, L. S. Smith, G. A. Soli, R. Y. Lo   +3 more
openaire   +1 more source

System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs)

2019
In this chapter, an efficient system-level approach to model and analyze the propagation of SEUs in a simple processor is introduced. The high-level model of the processor is formalized as a Continuous-Time Markov Chain (CTMC). Probabilistic model checking (PMC) is utilized to exhaustively estimate the impact of SEUs on the behavior of the processor ...
Marwan Ammar, Ghaith Bany Hamad, Otmane Ait Mohamed, Yvon Savaria   +3 more
openaire   +2 more sources