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Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained from Model Verification

IEEE Transactions on Nuclear Science, 1987
Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator ...
J. A. Zoutendyk   +3 more
openaire   +1 more source

Notice of Violation of IEEE Publication Principles: Selective Triple Modular Redundancy for Single Event Upset (SEU) Mitigation

2009 NASA/ESA Conference on Adaptive Hardware and Systems, 2009
This paper represents a design technique for hardening circuits mapped onto FPGAs. An effective and simple algorithm for signal probabilities has been used to detect SEU (single event upset) sensitive gates for a given circuit. The circuit can be hardened against radiation effects by applying triple modular redundancy (TMR) technique to only these ...
Xiaoxuan She, P.K. Samudrala
openaire   +1 more source

Neutron Induced Single Event Upset (SEU) Testing of Commercial Memory Devices with Embedded Error Correction Codes (ECC)

2017 IEEE Radiation Effects Data Workshop (REDW), 2017
Results of neutron induced single event upset testing of devices with embedded error correction codes are described. Specifically, Cypress CY7C1061GE30-10BVXI and CY7C1061GE-10BVXI 16-Mbit Static Random Access Memories (SRAMs), and a memory system, consisting of a Tundra Tsi107 PowerPC Host Bridge interfacing with nine Micron MT48LC32M8A2TG-75ITD 256 ...
John M. Bird   +6 more
openaire   +1 more source

Single event upset (SEU): Diagnostic and error correction system for avioncs device

2009
In aerospace applications, Commercial-Off-The-Shelf (COTS) Field programmable Gate Array (FPGA) is becoming increasingly attractive by offering low-cost solutions, simplicity and flexibility. This research faces the problem of disturbance induced by high energy particles on electronic devices.
CIANI, LORENZO   +2 more
openaire   +1 more source

Diagnostic and error correction system for avionics devices in presence of single event upset (SEU)

2013
In aerospace applications, Commercial-Off-The-Shelf (COTS) Field programmable Gate Array (FPGA) is becoming increasingly attractive by offering low-cost solutions, simplicity and flexibility. This research faces the problem of disturbance induced by high energy particles on electronic devices.
CATELANI, MARCANTONIO, CIANI, LORENZO
openaire   +1 more source

Efficient protection of polar decoders against Single Event Upsets (SEUs) on user memories

Microelectronics Reliability, 2023
Dong Tian   +5 more
openaire   +1 more source

Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2022
Semiu A. Olowogemo   +4 more
openaire   +1 more source

Critical Charge Dependency of Single Event Upset (SEU) on the Supply Voltage in Nanometric CMOS SRAMs

2022 Iranian International Conference on Microelectronics (IICM), 2022
Masume Soleimaninia   +2 more
openaire   +1 more source

Single-Event-Upset (SEU) Mitigation Techniques for Routing Resources of SRAM-FPGA

International Journal of Advancements in Computing Technology, 2012
Cheng Gao -, Wei Guo -, Jiaoying Huang -
openaire   +1 more source

Single Event Latchup (SEL) and Single Event Upset (SEU) Evaluation of Xilinx 7nm Versalâ„¢ ACAP programmable logic (PL)

2021 IEEE Nuclear and Space Radiation Effects Conference (NSREC), 2021
Pierre Maillard   +3 more
openaire   +1 more source

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