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A single event transient detector in SRAM-based FPGAs
Ni Tianming +2 more
exaly +3 more sources
On-Chip Characterization of Single-Event Transient Pulsewidths [PDF]
A new on-chip single-event transient (SET) test structure has been developed to autonomously characterize the widths of random SET pulses. Simulation results show measurement granularity of 900 ps for a 1.5 mum technology and also indicate that the measurement granularity rapidly scales down with technology. Laser tests were used to demonstrate circuit
Ronald Schrimpf +2 more
exaly +2 more sources
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Single event transients in combinatorial circuits
Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05, 2005The single event upset (SEU) mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time consuming and must be performed for each different circuit topology, incident particle and track. This work presents an accurate and computer efficient analytical model for the evaluation of
Gilson I. Wirth +3 more
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Efficient analysis of single event transients
Journal of Systems Architecture, 2004The effects of charged particles striking VLSI circuits and producing single event transients (SETs) are becoming an issue for designers who exploit deep sub-micron technologies; efficient and accurate techniques for assessing their impact on VLSI designs are thus needed.
SONZA REORDA, Matteo, VIOLANTE, MASSIMO
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Single event transients in dynamic logic
Proceedings of the 19th annual symposium on Integrated circuits and systems design, 2006Radiation effects, like Single Event Transients (SET), are increasingly affecting integrated circuits as device dimensions are scaling down. With decreasing dimensions and supply voltages, the charge used to store information decreases, turning the circuits more sensitive to the transient currents generated by energetic particle hits.
Gilson I. Wirth +3 more
openaire +1 more source

