Results 1 to 10 of about 117,391 (253)
In triple-well PMOSFET transistor, a deep n+ well (DNW) is a process used to isolate the substrate noise, which can lead to changes in effect of single event transient (SET). In outer space, collision of cosmic energetic particles with sensitive nodes of
Jizuo Zhang +4 more
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Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions
Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects.
Ygor Q. Aguiar +6 more
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Investigation of Single-Event-Transient Effects Induced by Heavy-Ion in All-Silicon DG-TFET
The heavy-ion analysis is a single-event-effect (SEE) that produces a single-event-transient (SET) pulse of current. In this work, the analysis was done to observe the maximum impact of heavy-ions on a calibrated double-gate tunnel field-effect ...
Ashish Maurya +3 more
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BackgroundBipolar devices used in space radiation environment for a long time are simultaneously threatened by the total ionization dose (TID) effect and single event transient (SET), and there is a synergistic effect between TID and SET.
CAI Jiao +8 more
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Investigation of Radiation Effects on FD-SOI Hall Sensors by TCAD Simulations
This work investigates the responses of the fully-depleted silicon-on-insulator (FD-SOI) Hall sensors to the three main types of irradiation ionization effects, including the total ionizing dose (TID), transient dose rate (TDR), and single event ...
Linjie Fan +3 more
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The single-event effect reliability issue is one of the most critical concerns in the context of space applications for SiC VDMOS. In this paper, the SEE characteristics and mechanisms of the proposed deep trench gate superjunction (DTSJ), conventional ...
Tao Liu +7 more
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This paper review presents Single Event Effects (SEE) irradiation tests under heavy ions of the test-chip of D-Flip-Flop (DFF) cells and complete readout integrated circuits (ROIC) as a function of temperature, down to 50 K.
Laurent Artola +9 more
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A fault-tolerant hardening-by-design frequency divider has been proposed for clock and data recovery in a 28-nm CMOS process. By means of the mandatory updating mechanism, the proposed divider can update the state of the D flip-flops from an error state ...
Hengzhou Yuan +5 more
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Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem.
Georgios Ioannis Paliaroutis +4 more
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This study investigates the AD574, a 12-bit analog/digital converter (ADC) produced by American Analog Devices, Inc. (ADI) using bipolar/I2L technology. The test samples are subjected to a total ionizing dose (TID) of 400 Gy(Si) under 60Co γ irradiation.
XIANG Chuanfeng +10 more
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