Results 201 to 210 of about 1,246 (262)

Inside the anger: development and validation of a new questionnaire. [PDF]

open access: yesBMC Psychiatry
Manfredi P   +3 more
europepmc   +1 more source

Internal Strengths for Adverse Life Events. [PDF]

open access: yesBehav Sci (Basel)
Zhao J, Chapman E, Houghton S.
europepmc   +1 more source

Measurements of Single Event Upset in ATLAS IBL

open access: yesMeasurements of Single Event Upset in ATLAS IBL
openaire  

Single event upset mitigation for FDP2008

2011 9th IEEE International Conference on ASIC, 2011
Highly integrated contemporary SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. In this paper, Fudan Design Environment (FDE) Triple Module Redundancy (TMR) approach for design triplication has been devised to meet high-reliability ...
Meng Yang, Gengsheng Chen
openaire   +1 more source

A Single Event Upset Resilient Latch Design with Single Node Upset Immunity

Journal of Electronic Testing, 2019
In this paper, a latch design with single node immunity to single event upsets during the hold state is proposed. This structure is based on the original Quatro latch and have two more redundant storage nodes. Compared with the reference, this structure is able to recover if any of these nodes is struck by ion particles during the hold state and it ...
Xixi Dai   +5 more
openaire   +1 more source

Single event upset in avionics

IEEE Transactions on Nuclear Science, 1993
Data from military/experimental flights and laboratory testing indicate that typical non-radiation-hardened 64 K and 256 K static random access memories (SRAMs) can experience a significant soft upset rate at aircraft altitudes due to energetic neutrons created by cosmic ray interactions in the atmosphere.
A. Taber, E. Normand
openaire   +1 more source

Estimating the effect of single-event upsets on microprocessors

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014
Evaluating the impact of single-event upsets (SEUs) on complex VLSI circuits in general, and microprocessors in particular, requires an interdisciplinary approach, that includes soft error modeling, accelerated measurements, derating of the raw error rates, and specialized design tools.
Cristian Constantinescu   +2 more
openaire   +1 more source

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