A CNTFET based process variation resilient SRAM design for stable low power and half select free operation. [PDF]
Sci RepHaq SU +5 more
europepmc +1 more source
3-Tier CFET 6T-SRAM with 2D-TMDs channels for Angstrom technology node. [PDF]
Sci RepLee J +5 more
europepmc +1 more source
A Low-Offset Sense Amplifier with Self-Adaptive Calibration and Dynamic Body-Biased Mitigation Technology for Enhanced SRAM Read Performance. [PDF]
Micromachines (Basel)Liu Y, Hu Y, Xiao H, Liu Y, Chen J.
europepmc +1 more source
SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction. [PDF]
Micromachines (Basel)Li T, Tian J, Qi J.
europepmc +1 more source
SNM Analysis & SRAM Based Memory Design
, 2017 In digital systems memory arrays are forming an integral building block. There are various aspects that need to be known to begin with the design of SRAM based memory and are vital for design of many other digital circuits. The integrated circuit that is
Ms, Akshdeepika
core
Algorithm-hardware co-design of neuromorphic networks with dual memory pathways. [PDF]
Nat Mach IntellSun P +5 more
europepmc +1 more source
, 2008 [[abstract]]本創作提出一種雙埠SRAM晶胞，其於讀取雙埠SRAM晶胞所儲存之資料後，無須對所讀取之資料再執行反相邏輯操作，該雙埠SRAM晶胞係包括一第一反相器(由第一PMOS電晶體P1與第一NMOS電晶體M1所組成)、一第二反相器(由第二PMOS電晶體P2與第二NMOS電晶體M1所組成)、一寫入用選擇電晶體(MWS)、一讀取用選擇電晶體(MRS)、一反相電晶體(MINV)、一寫入用字元線(WWL)、一讀取用字元線(RWL)、一寫入用位元線(WBL)以及一讀取用位元線(RBL)，其中 ...
蕭明椿
core
SRAM based Gaussian noise generation for post quantum cryptography. [PDF]
Sci RepKim MS, Jeon SB, Kim S.
europepmc +1 more source
Dual-directional CIM-based non-volatile SRAM for instant-on/off energy-constrained edge AI devices. [PDF]
Sci RepHemmasi SP +3 more
europepmc +1 more source
Empirical Evaluation of Unoptimized Sorting Algorithms on 8-Bit AVR Arduino Microcontrollers. [PDF]
Sensors (Basel)Golonka J, Krużel F.
europepmc +1 more source