Results 111 to 120 of about 17,373 (224)

Carbon Nanotube Based Variation Tolerant Low Power Cache Memory for 5G Networks [PDF]

Iranian Journal of Electrical and Electronic Engineering
The overall performance of any integrated circuit is defined by its proper memory design, as it is a mandatory and major block which requires more area and power.
Kavitha Manickam, P.K. Janani, S. Karthick, S. Arulsivam, C. Vikram, G. Hariharan, R. Kavinkumar, P. Ganesh   +7 more
doaj  

Non-imprinting high-speed erase SRAM IC design for low-power operation

, 2016
This report discusses the design and characterization process and result of a novel SRAM: Non-imprinting High-speed Erase SRAM (NIHE SRAM). By erasing data clearly and instantly, the developed NIHE SRAM can be used to store highly confidential ...
Bian, Jia Kun
core  

SRAM Characteristics as Physical Unclonable Functions

, 2009
The purpose of this project is to determine whether the initial contents of SRAM, when treated as a Physical Unclonable Function, are a reasonable choice for generating an encryption key for an FPGA configuration bitstream.
Chopra, Jatin, Colopy, Robyn L.
core   +1 more source

Retrospective Registration and Completer-Only Analysis Limit Confirmatory Claims of SRAM Superiority in Cervical Spondylosis [Letter]. [PDF]

J Pain Res
Yan J, Yang P, Su B.
europepmc   +1 more source

Stretching-Relaxation-Adjustment Manipulation versus Conventional Tuina for Non-Myelopathic Cervical Spondylosis: A Single-Blind Randomized Controlled Trial. [PDF]

J Pain Res
Zhang Y, Zheng G, Xu Y, Yuan L, Wang D, Tan D, Che J, Gao H, Dong Y.   +8 more
europepmc   +1 more source

Investigating the impact of irradiation on various ringFET-based SRAM circuits using 3D TCAD. [PDF]

Sci Rep
Anandhi R, Nagarajan KK, Ramya M.
europepmc   +1 more source

A CNTFET based process variation resilient SRAM design for stable low power and half select free operation. [PDF]

Sci Rep
Haq SU, Aminzadeh A, Darabi A, Abbasian E, Shah OA, Sreenivasulu VB.   +5 more
europepmc   +1 more source

3-Tier CFET 6T-SRAM with 2D-TMDs channels for Angstrom technology node. [PDF]

Sci Rep
Lee J, Lee J, Lee J, Ahn S, Jin D, Jeon J.   +5 more
europepmc   +1 more source

A Low-Offset Sense Amplifier with Self-Adaptive Calibration and Dynamic Body-Biased Mitigation Technology for Enhanced SRAM Read Performance. [PDF]

Micromachines (Basel)
Liu Y, Hu Y, Xiao H, Liu Y, Chen J.
europepmc   +1 more source

Monolithically integrating polarization-doped InGaN p-FET and GaN n-FET for complementary logic circuitry. [PDF]

Sci Adv
Yu J, Li T, Lao Y, Yang J, Cui J, Liu S, Yang H, Yin Y, Wang M, Yang X, Chen KJ, Shen B, Wei J.   +12 more
europepmc   +1 more source