Results 91 to 100 of about 13,836 (232)

SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits

2024 25th International Symposium on Quality Electronic Design (ISQED)
Designing the power delivery network (PDN) in very large-scale integrated (VLSI) circuits is increasingly important, especially for nowadays low-power integrated circuit (IC) design. In order to ensure that the designed PDN enables a low level of voltage drop and noise which is required for the success of IC design, accurate analysis of PDN is largely ...
Shan Shen, Zhiqiang Liu, Wenjian Yu
openaire   +2 more sources

A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

, 2008
This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have
Zhang Wancheng, Wu Nanjian
core  

(Be)sramna kultura

Crkva u Svijetu, 2016
Pri razmatranju problematike srama u članku su izdvojeni poj¬movi sram i stid (shame). Polazeći od jezične uporabe pojma, ovaj rad želi pokazati što se shvaća pod imenicom sram, odnosno stid, te kako je to bitno vezano uz naše tjelo, kao i uz zajednicu ...
Gordan Črpić, Krunoslav Novak
doaj  

Comprehensive performance analysis of CMOS and CNTFET based 8T SRAM cell

Journal of Electronic Science and Technology
In recent years, carbon nanotube field effect transistor (CNTFET) has become an attractive alternative to silicon for designing high-performance, highly stable, and low-power static random access memory (SRAM).
Mahamudul Hassan Fuad, Md Faysal Nayan, Sheikh Shahrier Noor, Rahbaar Yeassin, Russel Reza Mahmud   +4 more
doaj   +1 more source

Low Power SRAM Memory System using Low Leak

, 2014
— SRAM memory is an essential building block ...
S. Y. Kulkarni, Vijayalaxmi C. Kalal, Asymmertic Sram Cell, Ravikumar K. I, Rajani H. P   +4 more
core  

Enhancing the SRAM PUF with an XOR Gate

Applied Sciences
This study focuses on designing enhanced Physically Unclonable Functions (PUFs) based on SRAM devices and improving the security of cryptographic systems.
Jack Garrard, Manuel Aguilar Rios, Bertrand Cambou   +2 more
doaj   +1 more source

SRAM precharge system for reducing write power

, 2023
This paper presents the static random access memory (SRAM) precharge system by using an equaliser and a sense circuit. Recent goals of designing SRAM are to reduce area, delay, and power, and to maintain standard data stability and writability.
M Chan (7790741), Hussain Mohammed Dipu Kabir (13067211)   +1 more
core  

Effects of CNT Diameter Variability on a CNFET-Based SRAM

In this paper we study the effects of Single Walled Carbon Nanotube (SWCNT) diameter variations on performance and stability of 6-T SRAM cells. Parametric and Monte Carlo simulations are performed for SRAM designs based on different SWCNT mean diameters.
Ahmadi, Arash, Zhong, Yue, Maharatna, Koushik, Shahidipour, Hamed   +3 more
core  

SOFT ERROR TOLERANT DESIGN OF STATIC RANDOM ACCESS MEMORY BITCELL

, 2015
Static Random Access Memories (SRAMs) are commonly used in most of electronics. Due to the scaling of silicon technologies, the soft errors induced by energetic particles are becoming a significant reliability concern.
Li, Lixiang
core  

SRAM precharge system for reducing write power

, 2015
This paper presents the static random access memory (SRAM) precharge system by using an equaliser and a sense circuit. Recent goals of designing SRAM are to reduce area, delay, and power, and to maintain standard data stability and writability.
Kabir, Hussain Mohammed Dipu, Chan, Mansun   +1 more
core   +1 more source