Results 91 to 100 of about 17,373 (224)
FPGA-based fault injection design for 16K-point FFT processor
The Journal of Engineering, 2019 There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits ...
Chuang-An Mao +4 more
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Nanowire Volatile RAM as an Alternative to SRAM
, 2015 Maintaining benefits of CMOS technology scaling is becoming challenging, primarily due to increased manufacturing complexities and unwanted passive power dissipations.
Moritz, C. A., Rahman, M., Khasanvis, S.
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, 2008 [[abstract]]本創作提出一種雙埠SRAM晶胞，其於讀取雙埠SRAM晶胞所儲存之資料後，無須對所讀取之資料再執行反相邏輯操作，該雙埠SRAM晶胞係包括一第一反相器(由第一PMOS電晶體P1與第一NMOS電晶體M1所組成)、一第二反相器(由第二PMOS電晶體P2與第二NMOS電晶體M1所組成)、一寫入用選擇電晶體(MWS)、一讀取用選擇電晶體(MRS)、一反相電晶體(MINV)、一寫入用字元線(WWL)、一讀取用字元線(RWL)、一寫入用位元線(WBL)以及一讀取用位元線(RBL)，其中 ...
蕭明椿
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Psychopathy and Depression as Predictors of the Satanic Syndrome
Open Theology, 2017 The aims of this research were to determine: (1) the existence of an internally consistent and valid latent construct of the Satanic syndrome, and (2) if psychopathy and depression are significant predictors of the Satanic syndrome within different sex ...
Šram Zlatko
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Analysis of 6T SRAM Cell in Different Technologies
, 2017 Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital
Siba Kumar Panda, Subhashree Rath
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, 2008 In this paper, we present Dynamic Voltage and Frequency Managed 256 x 64 SRAM block in 65nm technology, for frequency ranging from 100MHz to 1GHz.
Verkila, Satish Anand +2 more
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Low power design in 100 MHz embedded SRAM
, 2001 Low power design method is used in a 100MHz embedded SRAM. The embedded SRAM used in a FFT chip is divided into 16 blocks. Two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set
Wang DH +4 more
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, 2008 In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz.
Verkila, Satish Anand +2 more
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High Performance Data Aware (HPDA) SRAM cell for IoT applications [PDF]
, 2019 Low power and high performance of static random access memory (SRAM) are the main key issues and has become vital components in modern VLSI systems.The system power, performance and reliability can be significantly improved by controlling the power ...
Singh, Ajay Kumar +2 more
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, 2013 本实用新型属于电学领域，涉及了一种基于SRAM（静态存储器）架构FPGA复位电路。该复位电路包括FPGA以及复位芯片，其中，FPGA的配置成功标志信号管脚接口与复位芯片的复位输入端管脚连接；复位芯片的复位输出管脚与FPGA的一个全局时钟输入管脚连接 ...
王华伟 +4 more
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