Results 101 to 110 of about 13,836 (232)
Nanoscale SRAM Variability and Optimization [PDF]
, 2011 Robust SRAM design is one of the key challenges of process technology scaling. The steady pace of process technology scaling allows doubling memory array sizes, which requires thorough characterization of the impact of sources of process variability on ...
Toh, Seng Oon
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, 2015 This paper presents different low-leakage power Carbon NanoTube FET (CNTFET) based SRAM cells at nano technology. These SRAM cells are obtained by applying different circuit level leakage power reduction techniques called Sleep transistor, Forced stack ...
Somineni, Rajendra Prasad +2 more
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Low power design in 100 MHz embedded SRAM
, 2001 Low power design method is used in a 100MHz embedded SRAM. The embedded SRAM used in a FFT chip is divided into 16 blocks. Two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set
Wang DH +4 more
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A study on the effects of variability on performance of CNFET based digital circuits
, 2012 With the continuous trend of reducing feature sizes, and employing continuously smaller components on integrated circuits, new challenges arise on the way of silicon CMOS circuits and devices.
Shahidipour, Hamed
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Psychological Topics, 2019 Cilj je ovog istraživanja bio ispitati odnose između osjećaja srama zbog pijenja, ruminacija o pijenju, depresivnosti i alkoholne žudnje kod osoba s poremećajem upotrebe alkohola.
Nikola Babić
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A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs
, 2019 Spin Transfer Torque Magnetic RAM (STT-MRAM) is being extensively considered as a promising replacement for Last Level Caches (LLC), due to its high density, low leakage and non-volatility. However, writes to STT-MRAM are energy intensive and have a high
Christian Tenllado +19 more
core +1 more source
DESIGN AND PERFORMANCE COMPARISON OF AVERAGE 8T SRAM WITH EXISTING 8T SRAM CELLS
, 2015 This paper presents 8T SRAM cell by using various techniques. The conflicting design requirement of read versus write operation in a conventional 8T SRAM bit cell is eliminated using separate read/write access transistors The read stability and the write-
, Bini Joy, Sathia Priya.M, Akshaya.N Ruth Anita Shirley.D
core +1 more source
, 2013 本实用新型属于电学领域，涉及了一种基于SRAM（静态存储器）架构FPGA复位电路。该复位电路包括FPGA以及复位芯片，其中，FPGA的配置成功标志信号管脚接口与复位芯片的复位输入端管脚连接；复位芯片的复位输出管脚与FPGA的一个全局时钟输入管脚连接 ...
王华伟 +4 more
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Memory Design for FFT Processor in 3DIC Technology
, 2009 Computation of Fast Fourier Transform (FFT) of a sequence is an integral part for the Synthetic Aperture Radar (SAR). For FFT computations, there are a lot of data modification operations (multiplication and addition) involved.
Gonsalves, Kiran
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, 2020 AN ABSTRACT OF THE THESIS OFAPARNA REDDY KOTTE, for the Master of science degree in Electrical and Computer Engineering, presented on November 5,2020, at Southern Illinois University Carbondale. TITLE: MEMRISTOR BASED SRAM MAJOR PROFESSOR: Dr. Haniotokis
Kotte, Aparna Reddy
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