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68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI. [PDF]
Front NeurosciGuo L +15 more
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A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays. [PDF]
Sensors (Basel)Wang W, Li X, Chen L, Sun H, Zhang F.
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Subnanosecond flash memory enabled by 2D-enhanced hot-carrier injection. [PDF]
NatureXiang Y +7 more
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SRAM Gauge: SRAM Health Monitoring via Cells Race
2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2021By shrinking transistors' dimensions and, consequently, reducing the operating voltage in nano-scale CMOS technologies, the stability of SRAM cells has become a major reliability concern. SRAM cells' robustness against undesirable bit-flips is commonly measured by Static Noise Margin (SNM). Degradation in SNM is mainly because of the gradual variations
Nezam Rohbani, Masoumeh Ebrahimi
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2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS), 2021
As technology advances and becomes increasingly smaller in scale, it makes performance and reliability a constant problem. Effects such as process variations (P), power-supply voltage variations (V), temperature variations (T) and aging (A) variations (PVTA - Process, Voltage, Temperature and Aging) are key parameters that affect circuit's performance ...
Jorge Semião +2 more
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As technology advances and becomes increasingly smaller in scale, it makes performance and reliability a constant problem. Effects such as process variations (P), power-supply voltage variations (V), temperature variations (T) and aging (A) variations (PVTA - Process, Voltage, Temperature and Aging) are key parameters that affect circuit's performance ...
Jorge Semião +2 more
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Proceedings of the 2019 Great Lakes Symposium on VLSI, 2019
We present an in-memory computing SRAM macro for binary neural networks. The memory macro computes XNOR-and-accumulate for binary/ternary deep convolutional neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay-product than digital ASIC and achieves high accuracy in machine learning ...
Zhewei Jiang +3 more
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We present an in-memory computing SRAM macro for binary neural networks. The memory macro computes XNOR-and-accumulate for binary/ternary deep convolutional neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay-product than digital ASIC and achieves high accuracy in machine learning ...
Zhewei Jiang +3 more
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NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors
IEEE Journal of Solid-State Circuits, 2001This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the ...
T. Miwa +9 more
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Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells
IEEE Transactions on Electron Devices, 2019We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling 6144 p- and n-type CNFETs), with all 1024 cells functioning ...
Pritpal S. Kanhaiya +4 more
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