Results 51 to 60 of about 55,126 (212)
Advanced Intelligent Systems, EarlyView.This study investigates the neuromorphic plasticity behavior of 180 nm bulk complementary metal oxide semiconductor (CMOS) transistors at cryogenic temperatures. The observed hysteresis data reveal a signature of synaptic behavior in CMOS transistors at 4 K.
Fiheon Imroze +8 more
wiley +1 more source
e-Prime: Advances in Electrical Engineering, Electronics and EnergyThe demand for enhancing the performance of reliable processors necessitates using dependable, energy-efficient, and high-speed memory. Multiple obstacles arise as a consequence of this enhancement at lower technological nodes.
M. Srinu +2 more
doaj +1 more source
Sensitive Volume Modeling in Calculation of Space Radiation-Induced SEU Cross Section [PDF]
فصلنامه علوم و فناوری فضایی, 2014 Shape and size of sensitive volume are the most important parameters to model electronic devices for calculation of the SEU rate from space radiations. So far different models have been proposed for estimation of the sensitive volume.
S. Boorboor, S. A. H. Feghhi, H. Jafari
doaj
Low-power adiabatic 9T static random access memory
The Journal of Engineering, 2014 In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses.
Yasuhiro Takahashi +3 more
doaj +1 more source
Design Of 1K Asynchronous Static Random Access Memory Using 0.35 Micron Complementary Metal Oxide Semiconductor Technology [PDF]
, 2005 Static Random Access Memory (SRAM) is a high speed semiconductor memory which is widely used as cache memory in microprocessors and microcontrollers, telecommunication and networking devices.
Yeong, Tak Nging
core
Advanced Intelligent Systems, EarlyView.A charge‐domain ternary content‐addressable memory using one capacitor one nanoelectromechanical memory switch (1C‐1N TCAM) is proposed for energy‐efficient, high‐reliability computations. Integrated with the back‐end‐of‐line process, the 1C‐1N TCAM leverages the air gap capacitance to achieve a high capacitance ratio and ternary functionality.
Jin Wook Lee +5 more
wiley +1 more source
Design of the two-tier MUX in 65 nm SRAM(65 nm SRAM两级多路选择器的设计)
Zhejiang Daxue xuebao. Lixue ban, 2010 为提高SRAM的存取速度,节省芯片面积,抑制工艺波动的影响,在对SRAM多路选择架构研究基础上改进了一种应用于65 nm SRAM的多路选择架构,建立了此多路选择架构的小信号模型.采用蒙特卡罗仿真导出了位线传输管的最小尺寸限制.同时,提出一种简单的估算电路节点时间常数的方法,用于从理论上分析改进的两级架构相对于传统的一级架构的优势,即当两级架构的两级译码的特征数字相近时可取得最佳性能,且灵敏放大器的特征数字越大时两级架构的优势越明显.仿真验证的结果显示,在面积几乎不变、控制复杂性几乎不增加前提下 ...
ZHANGQiang(张强), WUXiao-bo(吴晓波)
doaj +1 more source
Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications
Journal of Electrical and Computer Engineering, 2023 Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue ...
M. V. Nageswara Rao +6 more
doaj +1 more source
Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation
IEEE Access, 2021 Near-threshold voltage ( $V_{th}$ ) operation is an effective method for lowering energy consumption. However, it increases the impact of $V_{th}$ variation significantly, which makes it difficult for previously proposed static random access memory ...
Ji Sang Oh +4 more
doaj +1 more source
Advanced Intelligent Systems, EarlyView.Large‐scale Hopfield neural networks (HNNs) for associative computing are implemented using vertical NAND (VNAND) flash memory. The proposed VNAND HNN with the asynchronous update scenario achieve robust image restoration performance despite fabrication variations, while significantly reducing chip area (≈117× smaller than resistive random‐access ...
Jin Ho Chang +4 more
wiley +1 more source