Results 41 to 50 of about 13,836 (232)

Efficient In‐Hardware Matrix–Vector Multiplication and Addition Exploiting Bilinearity of Schottky Barrier Transistors Processed on Industrial FDSOI

Advanced Electronic Materials, EarlyView.
ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez, Niladri Bhattacharjee, Yuxuan He, Giulio Galderisi, Brojogopal Sapui, Sara Mannaa, Ian O'Connor, Violetta Sessi, Peter Javorka, Thomas Mikolajick, Jens Trommer   +10 more
wiley   +1 more source

Design of low power SRAM cells with increased read and write performance using Read - Write assist technique

e-Prime: Advances in Electrical Engineering, Electronics and Energy
The demand for enhancing the performance of reliable processors necessitates using dependable, energy-efficient, and high-speed memory. Multiple obstacles arise as a consequence of this enhancement at lower technological nodes.
M. Srinu, E. Sreenivasa Rao, P. Chandra Sekhar   +2 more
doaj   +1 more source

A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor

Micromachines, 2022
A monolithic three-dimensional integrated static random access memory containing a feedback field effect transistor (M3D-FBFET-SRAM) was proposed. The M3D-FBFET-SRAM cell consists of one metal oxide semiconductor field effect transistor (MOSFET) and one ...
Jong Hyeok Oh, Yun Seop Yu
doaj   +1 more source

Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

Advanced Intelligent Discovery, EarlyView.
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj, Ella Paasio, Sayani Majumdar   +2 more
wiley   +1 more source

Suočavanje s krivnjom i sramom

Diacovensia, 2017
Prepoznavati osjećaje koji otežavaju uspostavljanje odnosa s drugima važno je za psihičko i duhovno blagostanje osobe jer kada se upoznamo s njima i postajemo svjesni kako utječu na život, moguće ih je mijenjati radi punijega odnosa s drugima.
Josip Bošnjaković
doaj   +1 more source

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Journal of Electrical and Computer Engineering, 2023
Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue ...
M. V. Nageswara Rao, Mamidipaka Hema, Ramakrishna Raghutu, Ramakrishna S. S. Nuvvula, Polamarasetty P. Kumar, Ilhami Colak, Baseem Khan   +6 more
doaj   +1 more source

Hardware‐Based On‐Chip Learning Using a Ferroelectric AND‐Type Array With Random Synaptic Weights

Advanced Intelligent Systems, EarlyView.
This work demonstrates an energy‐efficient on‐chip learning system using an Metal‐Ferroelectric‐Insulator‐Semiconductor FeAND synaptic array. By employing a feedback alignment scheme with a separate backward array using fixed random weights, the system overcomes directional limitations of AND‐type arrays and achieves robust, low‐power learning suitable
Minsuk Song, Changhyeon Han, Joonhyeok Choi, Jongwoo Lee, Hyun‐min Kim, Wongi Hong, Ujin Kim, Sung‐Tae Lee, Daewoong Kwon   +8 more
wiley   +1 more source

March CRF: an Efficient Test for Complex Read Faults in SRAM Memories

, 2007
In this paper we study Complex Read Faults in SRAMs, a combination of various malfunctions that affect the read operation in nanoscale memories. All the memory elements involved in the read operation are studied, underlining the causes of the realistic ...
Luigi Dilillo, Al-Hashimi, B M, Bashir M. Al-Hashimi, Dilillo, Luigi, Dilillo, L, Hashimi, Bashir M. Al   +5 more
core   +1 more source

A Memristor‐Based In‐Memory Computing System‐on‐Chip with Efficient Depthwise Convolution

Advanced Intelligent Systems, EarlyView.
We present a memristor‐based in‐memory computing (IMC) architecture that enables efficient depthwise convolution (DWC) acceleration. Fabricated in a system‐on‐chip with crossbar arrays, the design improves memory utilization. Experimental validation demonstrates the first hardware acceleration of DWC in IMC, achieving a digital comparable inference ...
Wenhao Song, Fuxi Cai, Sangsu Park, Zhaoyan Li, Seonghun Lee, Mingyi Rao, Woohyung Choi, Seungin Shin, Yan Zhu, Sujin Chae, Myoungsub Kim, Mingche Wu, Hyejung Choi, Yuan Dao, Jaeyun Yi, Youngman Cho, Seon Yong Cha, Ning Ge, Qiangfei Xia, Soo Gil Kim, Miao Hu, J. Joshua Yang   +21 more
wiley   +1 more source

Design and Test of Principle Prototype of Space Single Event Upset Discriminating and Positioning System

Yuanzineng kexue jishu, 2022
Single event upset (SEU) has always been an important factor affecting the reliability of spacecraft electronic equipment, which can cause anomalies in electronic equipment in orbit, and can result in serious spacecraft failure. In order to master signal
ZHAO Zhendong;TAO Wenze;LI Yancun;CHENG Yi;ZHANG Qingxiang;AN Heng;QUAN Xiaoping;ZHANG Chenguang
doaj