Results 31 to 40 of about 13,883 (233)
SRAM Write-Ability Improvement with Transient Negative Bit-Line Voltage [PDF]
, 2019 Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell ...
SRAM Write-Ability Improvement with Transient Negative Bit-L +3 more
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Design of half-select free 12T SRAM cell with high performance for health care applications
e-Prime: Advances in Electrical Engineering, Electronics and EnergyStatic Random Access Memory (SRAM) plays a crucial role in applications related to health like Body Area Networks (BANs) which require increased battery lives for the sensor nodes in BANs.
Manoj Kumar R․ +1 more
doaj +1 more source
Automating defects simulation and fault modeling for SRAMs [PDF]
, 2008 The continues improvement in manufacturing process density for very deep sub micron technologies constantly leads to new classes of defects in memory devices. Exploring the effect of fabrication defects in future technologies, and identifying new classes
Stefano Di Carlo +9 more
core +1 more source
Low-power adiabatic 9T static random access memory
The Journal of Engineering, 2014 In this paper, the authors propose a novel static random access memory (SRAM) that employs the adiabatic logic principle. To reduce energy dissipation, the proposed adiabatic SRAM is driven by two trapezoidal-wave pulses.
Yasuhiro Takahashi +3 more
doaj +1 more source
Advanced Materials, EarlyView.We demonstrate a neuromorphic synapse in 2D Fe3GaTe2 flakes. The device operates via a current‐driven transformation from a skyrmion‐lattice to a stripe‐domain state, yielding a linear anomalous Hall resistance response with a tunable slope to enable multiply‐accumulate operations. Simulations confirm its viability in artificial neural networks.
Jixiang Huang +20 more
wiley +1 more source
Células SRAM de ultra baixa tensão com polarização de substrato [PDF]
, 2008 Dissertação (Mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-graduação em Engenharia ElétricaEsta dissertação visa o estudo da célula SRAM de 6 transistores, utilizando tecnologia CMOS convencional, operando em ...
Lima, Alessandro de Souza
core
Advanced Materials, EarlyView.ABSTRACT The accelerating expansion of data‐centric technologies is sharply increasing the energy burden of information storage, placing unprecedented pressure on the efficiency of magnetic switching. Conventional field‐driven reversal, once the foundation of magnetic memory, has become impractical in modern architectures due to its high energy cost ...
Mohammad H. Badarneh +2 more
wiley +1 more source
Leakage Read Fault in Nanoscale SRAM: Analysis, Test and Diagnosis [PDF]
, 2006 In this paper we study the impact of leakage currents on the operation of SRAM memories fabricated using nanoscale technologies. We show how the leakage currents, flowing through the pass transistors of unselected cells, may affect the read operation ...
Girard, Patrick +4 more
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Minimizing Test Power in SRAM through Reduction of Pre-charge Activity [PDF]
, 2006 In this paper we analyze the test power of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this observation in order to minimize power
Girard, Patrick +11 more
core +1 more source
Advanced Materials, EarlyView.The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj +8 more
wiley +1 more source