Results 11 to 20 of about 17,373 (224)

Radiation tolerant capacitor-SRAM without area overhead

Nuclear Engineering and Technology
In memory semiconductors such as a static random access memory (SRAM), a common problem is soft errors under radiation environment. These soft errors cause bit flips, which are referred to as single event upsets (SEUs). Some radiation-hardened SRAM cells
Eunju Jo, Hosang Yoon, Hongjoon Park, Woo-young Choi, Inyong Kwon   +4 more
doaj   +2 more sources

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

Nanoscale Research Letters, 2017
This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application.
Meng-Yin Hsu, Chu-Feng Liao, Yi-Hong Shih, Chrong Jung Lin, Ya-Chin King   +4 more
doaj   +2 more sources

Design and Analysis of Three New SRAM Cells

Majlesi Journal of Electrical Engineering
Three new SRAM cells are proposed in this paper. Increasing area overhead is the major concern in SRAM design. One of the new structures is included four transistors instead of six transistors as it is used in conventional 6T-SRAM cell for very high ...
Amir Ebrahimi, Ehsan Kargaran, Abbas Golmakani   +2 more
doaj   +1 more source

Reducing Power Dissipation in SRAM during Test [PDF]

, 2006
In this paper we analyze the power consumption of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test because of the predictable addressing sequence.
Girard, Patrick, Rosinger, Paul, Dilillo, Luigi, Al-Hashimi, Bashir M., Al-Hashimi, Bashir   +4 more
core   +2 more sources

Impact of random dopant induced fluctuations on sub-15nm UTB SOI 6T SRAM cells [PDF]

, 2005
The CMOS scaling increases the impact of intrinsic parameter fluctuation on the yield and functionality of SRAM. A statistical circuit simulation framework which can fully capture intrinsic parameter fluctuation information into the compact model has ...
Samsudin, K., Cheng, B., Brown, A.R., Asenov, A., Roy, S., A. Asenov, A.R. Brown, B. Cheng, S. Roy, K. Samsudin   +9 more
core   +1 more source

Performance evaluation of SRAM design using different field effect transistors [PDF]

E3S Web of Conferences, 2023
SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it.
C. Venkataiah, Y. Mallikarjuna Rao, Jayamma Manjula, M.K. Linga Murthy, S. Feroz Shah Ahmed, Alzubaidi Laith H.   +5 more
doaj   +1 more source

Performance analysis of OTFT-based SRAM topologies

Memories - Materials, Devices, Circuits and Systems, 2023
In terms of mechanical flexibility, organic SRAM offers better designs and a commercially feasible option with the ability to deliver acceptable performance.
Taniza Marium, S.M. Ishraqul Huq, Oli Lowna Baroi, Md. Shaikh Abrar Kabir, Satyendra N. Biswas   +4 more
doaj   +1 more source

The impact of random doping effects on CMOS SRAM cell [PDF]

, 2004
The SRAM has a very constrained cell area and is consequently sensitive to the intrinsic parameter fluctuations ubiquitous in decananometer scale MOSFETs.
Cheng, B., Asenov, A., Roy, S., A. Asenov, B. Cheng, S. Roy   +5 more
core   +1 more source

Timing speculative SRAM

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017
Static Random Access Memories (SRAMs) are considered a major bottleneck in high performance System-on-Chip (SoC) design and there is a large demand for high performance SRAMs with minimal energy consumption. Time speculation techniques such as Razor ease timing guardbands to improve performance or reduce energy consumption.
Elnaz Ebrahimi 0001, Matthew R. Guthaus, Jose Renau   +2 more
openaire   +4 more sources

Embedded intelligent SRAM [PDF]

Proceedings of the 40th conference on Design automation - DAC '03, 2003
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near the on-chip SRAM. The computation unit can perform operations on two words from the same SRAM row or
Prabhat Jain, G. Edward Suh, Srinivas Devadas   +2 more
openaire   +2 more sources