Results 11 to 20 of about 13,883 (233)
Performance evaluation of SRAM design using different field effect transistors [PDF]
E3S Web of Conferences, 2023 SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it.
C. Venkataiah +5 more
doaj +1 more source
Impact of random dopant induced fluctuations on sub-15nm UTB SOI 6T SRAM cells [PDF]
, 2005 The CMOS scaling increases the impact of intrinsic parameter fluctuation on the yield and functionality of SRAM. A statistical circuit simulation framework which can fully capture intrinsic parameter fluctuation information into the compact model has ...
Samsudin, K. +4 more
core +1 more source
Občutljivost za sram in njeni korelati pri parih
Psihološka Obzorja, 2010 Raziskava preučuje povezanost med tremi lestvicami instrumenta TOSCA-3 (občutljivost za sram, občutljivost za krivdo ter eksternalizacija) ter stresom, depresivnostjo, strahom pred intimo in stilom navezanosti pri 68 heteroseksualnih parih v trajnih ...
Tomaž Erzar +2 more
doaj +1 more source
UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation [PDF]
, 2005 Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs.
Samsudin, K. +4 more
core +1 more source
The impact of random doping effects on CMOS SRAM cell [PDF]
, 2004 The SRAM has a very constrained cell area and is consequently sensitive to the intrinsic parameter fluctuations ubiquitous in decananometer scale MOSFETs.
Cheng, B., Asenov, A., Roy, S.
core +1 more source
Performance analysis of OTFT-based SRAM topologies
Memories - Materials, Devices, Circuits and Systems, 2023 In terms of mechanical flexibility, organic SRAM offers better designs and a commercially feasible option with the ability to deliver acceptable performance.
Taniza Marium +4 more
doaj +1 more source
Reducing Power Dissipation in SRAM during Test [PDF]
, 2006 In this paper we analyze the power consumption of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test because of the predictable addressing sequence.
Girard, Patrick +4 more
core +1 more source
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017 Static Random Access Memories (SRAMs) are considered a major bottleneck in high performance System-on-Chip (SoC) design and there is a large demand for high performance SRAMs with minimal energy consumption. Time speculation techniques such as Razor ease timing guardbands to improve performance or reduce energy consumption.
Elnaz Ebrahimi 0001 +2 more
openaire +3 more sources
Embedded intelligent SRAM [PDF]
Proceedings of the 40th conference on Design automation - DAC '03, 2003 Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near the on-chip SRAM. The computation unit can perform operations on two words from the same SRAM row or
Prabhat Jain +2 more
openaire +1 more source
Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells [PDF]
, 2008 The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors.
Stefano Di Carlo +7 more
core +1 more source