Results 51 to 60 of about 13,836 (232)
NOVEL IN-MEMORY COMPUTING CIRCUIT USING MULLER-C ELEMENT [PDF]
Proceedings on Engineering SciencesThe proposed research work addresses the von Neumann bottleneck, a limitation in computing systems where data transfer between memory and processor components slows down performance.
Gururaj A Tapashetti , Umadevi S
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An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache
IEEE Access, 2020 An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance ...
Tae Hyun Kim +5 more
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Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation
IEEE Access, 2021 Near-threshold voltage ( $V_{th}$ ) operation is an effective method for lowering energy consumption. However, it increases the impact of $V_{th}$ variation significantly, which makes it difficult for previously proposed static random access memory ...
Ji Sang Oh +4 more
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WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays [PDF]
Journal of Low Power Electronics, 2004 The increasing sub-threshold leakage current levels with newer technology nodes have been identified by ITRS (2001) as one of the major fundamental problems faced by the semiconductor industry. Concurrently, the expected performance improvement and functionality integration expectations drive the continued reduction in feature size.
Mahadevan Gomathisankaran +1 more
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Advanced Intelligent Systems, EarlyView.This article introduces an input sparsity‐aware computing‐in‐memory macro featuring novel bidirectional conversion‐skippable analog‐to‐digital converters. By dynamically adjusting resolution based on element‐level sparsity, the architecture skips redundant most significant bit and least significant bit conversions.
Choongseok Song +2 more
wiley +1 more source
In‐Memory Continuous‐Time SAT Solver Based on Bidirectional 11‐T SRAM Macro
Advanced Intelligent Systems, EarlyView.This article reported a continuous‐time (CT) Boolean satisfiability (SAT) problem solver using bidirectional 11T‐SRAM macro. The proposed system operates asynchronously using capacitor‐based gradient integration and maximizes the parallelism for SAT solving by in‐memory computing (IMC).
Dongseok Kwon +3 more
wiley +1 more source
Design of the two-tier MUX in 65 nm SRAM(65 nm SRAM两级多路选择器的设计)
Zhejiang Daxue xuebao. Lixue ban, 2010 为提高SRAM的存取速度,节省芯片面积,抑制工艺波动的影响,在对SRAM多路选择架构研究基础上改进了一种应用于65 nm SRAM的多路选择架构,建立了此多路选择架构的小信号模型.采用蒙特卡罗仿真导出了位线传输管的最小尺寸限制.同时,提出一种简单的估算电路节点时间常数的方法,用于从理论上分析改进的两级架构相对于传统的一级架构的优势,即当两级架构的两级译码的特征数字相近时可取得最佳性能,且灵敏放大器的特征数字越大时两级架构的优势越明显.仿真验证的结果显示,在面积几乎不变、控制复杂性几乎不增加前提下 ...
ZHANGQiang(张强), WUXiao-bo(吴晓波)
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NCFET-Based 6-T SRAM: Yield Estimation Based on Variation-Aware Sensitivity
IEEE Journal of the Electron Devices Society, 2020 The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS) <; 60 mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and passgate (PG) transistor in six-transistor (6T) SRAM bit-cell ...
Yuri Hong, Yejoo Choi, Changhwan Shin
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Neuromorphic Denoising with Fully Analog Memristive In‐Memory Computing
Advanced Intelligent Systems, EarlyView.This article borrows the concepts of episodic memory in human brains to experimentally implement a memristor‐based neuromorphic denoising process. A homogeneous memristor processing unit is experimentally demonstrated for both temporal storage and neural network computation, imitating the synapses in the human brain.
Daijing Shi +5 more
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SRAM Write-Ability Improvement with Transient Negative Bit-Line Voltage
, 2019 Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell ...
SRAM Write-Ability Improvement with Transient Negative Bit-L +3 more
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