Results 51 to 60 of about 55,876 (211)

Emerging Memory and Device Technologies for Hardware‐Accelerated Model Training and Inference

Advanced Electronic Materials, EarlyView.
This review investigates the suitability of various emerging memory technologies as compute‐in‐memory hardware for artificial intelligence (AI) applications. Distinct requirements for training‐ and inference‐centric computing are discussed, spanning device physics, materials, and system integration.
Yoonho Cho, Dae‐won Kim, Yujin Kim, Jung‐Heum Na, Yuwon Jeong, Dong‐Yeop Lee, Shinhyun Choi   +6 more
wiley   +1 more source

Design of low power SRAM cells with increased read and write performance using Read - Write assist technique

e-Prime: Advances in Electrical Engineering, Electronics and Energy
The demand for enhancing the performance of reliable processors necessitates using dependable, energy-efficient, and high-speed memory. Multiple obstacles arise as a consequence of this enhancement at lower technological nodes.
M. Srinu, E. Sreenivasa Rao, P. Chandra Sekhar   +2 more
doaj   +1 more source

Efficient In‐Hardware Matrix–Vector Multiplication and Addition Exploiting Bilinearity of Schottky Barrier Transistors Processed on Industrial FDSOI

Advanced Electronic Materials, EarlyView.
ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez, Niladri Bhattacharjee, Yuxuan He, Giulio Galderisi, Brojogopal Sapui, Sara Mannaa, Ian O'Connor, Violetta Sessi, Peter Javorka, Thomas Mikolajick, Jens Trommer   +10 more
wiley   +1 more source

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache

IEEE Access, 2020
An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance ...
Tae Hyun Kim, Hanwool Jeong, Juhyun Park, Hoonki Kim, Taejoong Song, Seong-Ook Jung   +5 more
doaj   +1 more source

Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS

, 2017
Many modern video processing pipelines rely on edge-aware (EA) filtering methods. However, recent high-quality methods are challenging to run in real-time on embedded hardware due to their computational load. To this end, we propose an area-efficient and
Benini, Luca, Cavigelli, Lukas, Eggimann, Manuel, Gloor, Christelle, Schaffner, Michael, Scheidegger, Florian, Smolic, Aljosa   +6 more
core   +1 more source

Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

Advanced Intelligent Discovery, EarlyView.
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj, Ella Paasio, Sayani Majumdar   +2 more
wiley   +1 more source

Multi-port Memory Design for Advanced Computer Architectures [PDF]

, 2013
In this thesis, we describe and evaluate novel memory designs for multi-port on-chip and off-chip use in advanced computer architectures. We focus on combining multi-porting and evaluating the performance over a range of design parameters.
Zhao, Yirong
core  

Hardware‐Based On‐Chip Learning Using a Ferroelectric AND‐Type Array With Random Synaptic Weights

Advanced Intelligent Systems, EarlyView.
This work demonstrates an energy‐efficient on‐chip learning system using an Metal‐Ferroelectric‐Insulator‐Semiconductor FeAND synaptic array. By employing a feedback alignment scheme with a separate backward array using fixed random weights, the system overcomes directional limitations of AND‐type arrays and achieves robust, low‐power learning suitable
Minsuk Song, Changhyeon Han, Joonhyeok Choi, Jongwoo Lee, Hyun‐min Kim, Wongi Hong, Ujin Kim, Sung‐Tae Lee, Daewoong Kwon   +8 more
wiley   +1 more source

WARM SRAM: A Novel Scheme to Reduce Static Leakage Energy in SRAM Arrays [PDF]

Journal of Low Power Electronics, 2004
The increasing sub-threshold leakage current levels with newer technology nodes have been identified by ITRS (2001) as one of the major fundamental problems faced by the semiconductor industry. Concurrently, the expected performance improvement and functionality integration expectations drive the continued reduction in feature size.
Mahadevan Gomathisankaran, Akhilesh Tyagi   +1 more
openaire   +1 more source

Input Sparsity‐Aware Computing‐In‐Memory with Bidirectional Conversion‐Skippable Analog‐to‐Digital Converter

Advanced Intelligent Systems, EarlyView.
This article introduces an input sparsity‐aware computing‐in‐memory macro featuring novel bidirectional conversion‐skippable analog‐to‐digital converters. By dynamically adjusting resolution based on element‐level sparsity, the architecture skips redundant most significant bit and least significant bit conversions.
Choongseok Song, Yonguk Sim, Doo Seok Jeong   +2 more
wiley   +1 more source