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Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits [PDF]
We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of
G. Lakshmi Priya +5 more
doaj +2 more sources
Performance Analysis Of SRAM and Dram in Low Power Application [PDF]
All electronic systems must function quickly in the current environment, and 80 percent of electronic chips have memory components. SRAM (Static Random Access Memory) has thus become a major key component in many VLSI Chips in order to reduce the size of
Yuvaraj S. +5 more
doaj +1 more source
Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors
Summary: Driven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious.
Fan Wang +7 more
doaj +1 more source
A Noninvasive Technique to Detect Authentic/Counterfeit SRAM Chips
Many commercially available memory chips are fabricated worldwide in untrusted facilities. Therefore, a counterfeit memory chip can easily enter into the supply chain in different formats. Deploying these counterfeit memory chips into an electronic system can severely affect security and reliability domains because of their substandard quality, poor ...
B. M. S. Bahar Talukder +2 more
openaire +2 more sources
Validating foundry technologies for extended mission profiles [PDF]
This paper presents a process qualification and characterization strategy that can extend the foundry process reliability potential to meet specific automotive mission profile requirements.
Detcheverry, C. +6 more
core +12 more sources
SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview
Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical.
Waqas Gul +2 more
doaj +1 more source
With the percentage of embedded SRAM increasing in SoC chips, low-power design such as the near-threshold SRAM technique are getting increasing attention to reduce the entire chip energy consumption. However, the descending operating voltage will lead to
Uma Maheshwar Janniekode +1 more
doaj +1 more source
A Reconfigurable SRAM Based CMOS PUF With Challenge to Response Pairs
This paper presents a reconfigurable SRAM-based physically unclonable function (PUF) topology with multiple challenge-response pairs (CRPs) per cell. The proposed PUF structure enables a very large CRP space by connecting additional pull-up and pull-down
Seungbum Baek +5 more
doaj +1 more source
Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography [PDF]
AbstractIn today’s globalized integrated circuit (IC) ecosystem, untrusted foundries are often procured to build critical systems since they offer state-of-the-art silicon with the best performance available. On the other hand, ICs that originate from trusted fabrication cannot match the same performance level since trusted fabrication is often ...
Ioannis Karageorgos +3 more
openaire +1 more source
Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure
Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers,
Xu Zhang +9 more
doaj +1 more source

