Binary-Weighted Neural Networks Using FeRAM Array for Low-Power AI Computing. [PDF]
Cho SM +5 more
europepmc +1 more source
Subnanosecond flash memory enabled by 2D-enhanced hot-carrier injection. [PDF]
Xiang Y +7 more
europepmc +1 more source
Automated Synthesis of Multi-Port Memories and Control [PDF]
Cirimelli-Low, Jesse +4 more
core +1 more source
Concealable physical unclonable functions using vertical NAND flash memory. [PDF]
Park SH +5 more
europepmc +1 more source
Oxide semiconductor gain cell-embedded memory: materials and integration strategies for next generation on-chip memory. [PDF]
Chung SW, Yoon SH, Jeong JK.
europepmc +1 more source
A review of SPAD array chip design for direct time-of-flight LiDAR. [PDF]
Mo L, Huang S, Yang Y, Ren TL.
europepmc +1 more source
High-performance ternary logic circuits and neural networks based on carbon nanotube source-gating transistors. [PDF]
Zhu X +11 more
europepmc +1 more source
A 316MP, 120FPS, High Dynamic Range CMOS Image Sensor for Next Generation Immersive Displays. [PDF]
Agarwal A +12 more
europepmc +1 more source
Transpose-free variable-size FFT accelerator based on-chip SRAM
Lei Guo +4 more
openaire +2 more sources
Secure ECDSA SRAM-PUF Based on Universal Single/Double Scalar Multiplication Architecture. [PDF]
Zhang J +8 more
europepmc +1 more source

