Results 21 to 30 of about 10,430 (199)
Design of 10T SRAM cell with improved read performance and expanded write margin
IET Circuits, Devices and Systems, 2021 The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes.
Ashish Sachdeva, V. K. Tomar
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Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA
IET Computers & Digital Techniques, 2021 Fault detection and diagnosis of a Field‐Programmable Gate Array (FPGA) in a short period is vital particularly in reducing the dead time of critical applications that are running on FPGAs.
T. Nirmalraj +2 more
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Wafer Burn-in Method of SRAM for Multi Chip Package [PDF]
Transactions on Electrical and Electronic Materials, 2004 This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality
Hoo-Sung Kim +2 more
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ACE16K: A 128×128 focal plane analog processor with digital I/O [PDF]
, 2002 This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level perspective, which has been manufactured in a 0.35 μm standard digital 1P-5M CMOS technology. The chip has been designed to achieve
Domínguez Castro, Rafael +3 more
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Marmote SDR: Experimental Platform for Low-Power Wireless Protocol Stack Research
Journal of Sensor and Actuator Networks, 2013 Over the past decade, wireless sensor network research primarily relied on highly-integrated commercial off-the-shelf radio chips. The rigid silicon implementation of the radio stack restricted access to the lower layers; thus, research focused mainly on
Ákos Lédeczi +3 more
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A committee machine gas identification system based on dynamically reconfigurable FPGA [PDF]
, 2008 This paper proposes a gas identification system based on the committee machine (CM) classifier, which combines various gas identification algorithms, to obtain a unified decision with improved accuracy.
Amira, A +4 more
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Wafer Burn-in Method for SRAM in Multi Chip Package [PDF]
Journal of the Korean Institute of Electrical and Electronic Material Engineers, 2005 This paper presents the improved burn-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved by the burn-in process. Reliability Problem is very significant in the MCP which includes over two chips in a package because the failure of one SRAM chip has a large influence on the yield and quality ...
Jee-Young Yoon +3 more
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DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC [PDF]
Journal of Engineering Science and Technology, 2014 Static Random Access Memory (SRAM) has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST) logic is proposed.
A. KISHORE KUMAR +3 more
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SRAM has no chill: exploiting power domain separation to steal on-chip secrets [PDF]
Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2022 The widespread use of embedded systems has increased the risk of physical memory disclosure attacks. A notable example is the cold boot attack, where attackers exploit DRAM’s temperature-dependent data retention property.
Jubayer Mahmod, Matthew Hicks
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FPGA-based fault injection design for 16K-point FFT processor
The Journal of Engineering, 2019 There are a number of satellites working in the harsh space environment. The charged particles in space may strike the electron devices causing the undesired influences, such as soft errors in memory devices or permanent damage in hardware circuits ...
Chuang-An Mao +4 more
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