Results 1 to 10 of about 156 (114)
IEEE Access, 2022 Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones.
Mehdi Takbiri +2 more
doaj +1 more source
IEEE Access, 2021 Despite the advantages of ternary logic, it has suffered from excessive transistor count and limited noise margin. This work proposes an ultra-efficient nonvolatile ternary flip-flop (FF) based on negative capacitance carbon nanotube field-effect ...
Mohammad Hossein Moaiyeri +3 more
doaj +1 more source
Micromachines, 2023 We comprehensively investigate displacement-defect-induced current and static noise margin variations in six-transistor (6T) static random access memory (SRAM) based on a 10 nm node fin field-effect transistor (FinFET) using technology computer-aided ...
Minji Bang +4 more
doaj +1 more source
Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell
Sensors, 2021 Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems.
Bharathi Raj Muthu +6 more
doaj +1 more source
Novel Ternary Logic Gates Design in Nanoelectronics
Advances in Electrical and Electronic Engineering, 2019 In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is ...
Sajjad Etezadi, Seied Ali Hosseini
doaj +1 more source
Modeling Static Noise Margin for FinFET based SRAM PUFs
2020 IEEE European Test Symposium (ETS), 2020 In this paper, we develop an analytical PUF model based on a compact FinFET transistor model that calculates the PUF stability (i.e. PUF static noise margin (PSNM)) for FinFET based SRAMs. The model enables a quick design space exploration and may be used to identify critical parameters that affect the PSNM. The analytical model is validated with SPICE
Shayesteh Masoumian +5 more
openaire +3 more sources
VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY
International Islamic University Malaysia Engineering Journal, 2011 This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness.
Aminul Islam, Mohd. Hasan
doaj +1 more source
Performance evaluation of SRAM design using different field effect transistors [PDF]
E3S Web of Conferences, 2023 SRAM (Static Random Access Memory) is one of the type of memory which holds the data bit without periodic refreshment. Compared with DRAM (Dynamic Random Access Memory) which requires periodic refreshment of data bit stored in it.
C. Venkataiah +5 more
doaj +1 more source
Single-ended 6T SRAM Cell with Low Power/Energy Consumption and High Stability [PDF]
AUT Journal of Electrical Engineering, 2022 In this paper, we propose 6T cell with single-ended characteristics to achieve an improved stability, decrease energy consumption, and decrease leakage power.
Javad Mohagheghi +2 more
doaj +1 more source
Journal of Low Power Electronics and Applications, 2017 In this paper, an ultra-low power (ULP) 10T static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates at sub-threshold voltage. The proposed SRAM has the tendency to operate at low supply voltages with high
Pooran Singh, Santosh Kumar Vishvakarma
doaj +1 more source