Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design
Journal of Nanotechnology, 2020 The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects ...
Mathan Natarajamoorthy +3 more
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On the Critical Role of Ferroelectric Thickness for Negative Capacitance Device-Circuit Interaction
IEEE Journal of the Electron Devices Society, 2021 This paper demonstrates the critical role that Ferroelectric (FE) layer thickness ( $t_{FE}$ ) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a
Om Prakash +4 more
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Static noise margin enhancement by flex‐pass‐gate SRAM
Electronics and Communications in Japan, 2008 AbstractA flex‐pass‐gate SRAM, that is, a fin‐type field effect transistor‐based (FinFET‐based) SRAM, is proposed to enhance the noise margin during both read and write operations. In its cell, the flip‐flop is composed of the usual three‐terminal (3T) FinFETs and the pass gates are composed of four‐terminal (4T) FinFETs.
O'uchi, Shin-ichi +8 more
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UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation [PDF]
, 2005 Intrinsic parameter fluctuations steadily increases with CMOS technology scaling. Around the 90nm technology node, such fluctuations will eliminate much of the available noise margin in SRAM based on conventional MOSFETs.
Samsudin, K. +9 more
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Sensors, 2021 An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications.
Ming-Hwa Sheu +5 more
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Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS
Alexandria Engineering Journal, 2020 Designing a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing density in integrated digital circuits.
Tara Ghafouri, Negin Manavizadeh
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Effects of total ionizing dose on transient ionizing radiation upset sensitivity of 40–180 nm SRAMs
AIP Advances, 2022 Effects of total ionizing dose (TID) on the transient radiation upset sensitivity of commercial static random access memories (SRAMs) were investigated.
Junlin Li +8 more
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Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM
Journal of Nanotechnology, 2017 CMOS technology below 10 nm faces fundamental limits which restricts its applicability for future electronic application mainly in terms of size, power consumption, and speed. In digital electronics, memory components play a very significant role.
Shital Joshi, Umar Alabawi
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Design and exploration of vertically stacked complementary tunneling field-effect transistors
Applied Physics Express, 2023 The purpose of this letter is to study the design and explore vertically stacked complementary tunneling field-effect transistors (CTFETs) using CFET technology for emerging technology nodes.
Narasimhulu Thoti, Yiming Li
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An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications
Journal of Low Power Electronics and Applications, 2014 Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC)
Arijit Banerjee, Benton H. Calhoun
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