Results 101 to 110 of about 17,853 (211)

Exploring the role of interfacial Dzyaloshinskii–Moriya interaction in write error rate anomalies of spin-transfer torque magnetic tunnel junctions

open access: yesnpj Spintronics
The performance and reliability of spin-transfer torque magnetic random-access memory (STT-MRAM) can be compromised by anomalous switching behavior, especially during high-speed operations.
Prosenjit Das   +2 more
doaj   +1 more source

Control of Sub-Nanosecond Precessional Magnetic Switching in STT-MRAM Cells for SRAM Applications

open access: yes, 2016
International audienceSTT-MRAM are foreseen as the best contender forDRAM replacement. STT-MRAM could also be used for SRAMapplications if switching time below 1ns could be realized in areliable way.
B. Dieny   +17 more
core   +1 more source

Description of statistical switching in perpendicular STT-MRAM within a numerical micromagnetic framework

open access: yes, 2017
The magnetization switching driven by spin-transfer torque (STT) and Spin Hall effect (SHE) is the fundamental dynamics to design magnetic memories and spin-logic devices.
V. Puliafito   +9 more
core   +1 more source

Controlling Bias Field of Pinned Layer Stacks for Double‐Pinned‐Layer Magnetic Tunnel Junction for STT‐MRAM

open access: yesAdvanced Electronic Materials
Double‐pinned‐layer Magnetic Tunnel Junction (Double PL MTJ) enhances spin‐transfer‐torque magneto‐resistive random‐access memory (STT‐MRAM) performance by requiring anti‐parallel magnetization between both PLs at free layer interfaces and minimizing ...
Shujun Ye, Koichi Nishioka
doaj   +1 more source

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

open access: yesIEEE Access
In recent years, the rapid growth of big data and the increasing demand for high-performance computing have fueled the development of novel computing architectures.
Alaba Yusuf   +2 more
doaj   +1 more source

Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement Policy

open access: yes, 2018
International audienceModern architectures adopt large on-chip cache memory hierarchies with more than two levels. While this improves performance, it has a certain cost in area and power consumption.
Bruguier, Florent   +11 more
core   +1 more source

Simulation of SAF-Enhanced Multilayered STT-MRAM Structures

open access: yes
The reliability of multilayered spin-transfer torque magnetoresistive random access memory with synthetic antiferro-magnets is critical for applications such as computing-in-memory systems, high-performance computing, and high-density storage. This study
Selberherr, Siegfried; orcid:   +3 more
core   +1 more source

Modelling and Circuit Design for STT-MRAM [PDF]

open access: yes, 2015
This thesis presents three research contributions in the areas of modelling, circuit-level design, and device-level design of spin-transfer-torque magnetoresistive random access memory (STT-MRAM).
Vatankhahghadim, Aynaz
core  

Enhanced write margin of perpendicular MRAM cells using thick MgO cap layer

open access: yesAIP Advances
Implementation of spin transfer torque magneto-resistive random access memory (STT-MRAM) in memory chips requires that the write margin of the MRAM cell, defined as the difference between breakdown voltage and write voltage for the specified endurance ...
G. Mihajlović   +4 more
doaj   +1 more source

Novel CPU cache architecture based on two-dimensional MTJ device with ferromagnetic Fe3GeTe2

open access: yesAIP Advances
With the development of Artificial Intelligence (AI) in recent years, the fields of computer, biology, medicine, and aerospace have demanded higher requirements for the processing and storage of information.
Shaopu Han, Yanfeng Jiang
doaj   +1 more source

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