Results 81 to 90 of about 12,742 (221)
Towards reliability of SNNs: defect implementation on STT-MRAM cell
International audienceSpiking Neural Networks (SNNs) are being widely studied to mimic the intelligence of biological brains. In hardware level, multiple emerging non-volatile memories (NVM) are proposed to model the neural synapses, one of them being ...
Vatajelu, Elena, Ioana +1 more
core
STT-MRAM characterization and its test implications [PDF]
Spin torque transfer (STT)-magnetoresistive random-access memory (MRAM) has come a long way in research to meet the speed and power consumption requirements for future memory applications. The state-of-the-art STT-MRAM bit-cells employ magnetic tunnel
Radhakrishnan, Govindakrishnan
core
Novel Self-timing Speculative Writing for Unreliable STT-MRAM
International audienceConsidering the insatiable demand for emerging embedded non-volatile memory (NVM), spin-transfer torque magnetic random access memory (STT-MRAM) can be configured with high access speed, readily hybrid integration and guaranteed ...
Cai, Hao +2 more
core +1 more source
As applications using deep neural networks (DNNs) are increasingly deployed on mobile devices, researchers are exploring various methods to achieve low energy consumption and high performance. Recently, advances in STT-MRAM have shown promise in offering
Munhyung Lee +3 more
doaj +1 more source
MODELING OF MTJ AND ITS VALIDATION USING NANOSCALE MRAM BITCELL [PDF]
Magnetic Tunnel Junction (MTJ) is a promising candidate for nonvolatile and low power memory design. MTJ is basic building block of STT-MRAM bitcell.
CHANDRAMAULESHWAR ROY +2 more
doaj
Standby magnetic immunity calculator for STT-MRAM [PDF]
This work investigates the impact of external magnetic fields, field orientation, temperature, and exposure time on the standby magnetic immunity (SMI) of spin-transfer torque magnetoresistive random-access memory. Wafer-level measurements were performed
A. Talapatra +7 more
doaj +1 more source
A Timing-Based Split-Path Sensing Circuit for STT-MRAM. [PDF]
Ishdorj B, Kim J, Kim JH, Na T.
europepmc +1 more source
Throughput-Efficient Network-on-Chip Router Design with STT-MRAM [PDF]
As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck in large-scale multicore ...
Narayana, Sagar 1986-
core
Survey of STT-MRAM Cell Design Strategies
Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density.
Deliang Fan +5 more
core +1 more source
Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario. [PDF]
Bian Z +5 more
europepmc +1 more source

