Results 71 to 80 of about 12,742 (221)

Multi-Port 1R1W Transpose Magnetic Random Access Memory by Hierarchical Bit-Line Switching

open access: yesIEEE Access, 2019
Emerging Magnetic Random-Access Memory (MRAM) has shown a great potential to replace Static-RAM (SRAM) and Dynamic-RAM (DRAM) in the working memories including Cache and main memory. MRAM benefits from its high-density, fast speed, low standby power, and
Liang Chang   +3 more
doaj   +1 more source

Analysis of Magnetic Switching in Magnetically Coupled Dual Free Layers Within Magnetic Tunnel Junctions (MTJ) for STT MRAM

open access: yesAdvanced Electronic Materials, Volume 12, Issue 5, 9 March 2026.
A magnetic tunnel junction (MTJ) with two free layers shows four magnetization reversal phases governed by interlayer magnetic coupling (Jcpl). Phase 2 (sequential reversal) reduces write current (Iw) by 50% for 30‐nm‐diameter MTJs compared to Phase 4 (coherent reversal), while Jcpl also boosts thermal stability.
Shujun Ye, Koichi Nishioka
wiley   +1 more source

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

open access: yes, 2018
Current main memory organizations in embedded and mobile application systems are DRAM dominated. The ever-increasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design.
Manu Komalan   +29 more
core   +1 more source

Triboelectric Tactile Transducers for Neuromorphic Sensing and Synaptic Emulation: Materials, Architectures, and Interfaces

open access: yesAdvanced Energy and Sustainability Research, Volume 7, Issue 3, March 2026.
Triboelectric nanogenerators are vital for sustainable energy in future technologies such as wearables, implants, AI, ML, sensors and medical systems. This review highlights improved TENG neuromorphic devices with higher energy output, better stability, reduced power demands, scalable designs and lower costs.
Ruthran Rameshkumar   +2 more
wiley   +1 more source

STT-MRAM Based NoC Buffer Design [PDF]

open access: yes, 2012
As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design.
Vikram Kulkarni, Nikhil
core  

Ferroelectric Tunnel Junction Memristor Crossbar Array with Annealing Optimization for In‐Memory Computing

open access: yesAdvanced Intelligent Systems, Volume 8, Issue 3, March 2026.
A 48 × 48 ferroelectric tunnel junction (FTJ) crossbar array is fabricated and optimized through postmetallization annealing, enabling stable polarization switching and reliable multilevel conductance programming. Half‐bias operation, accurate vector–matrix multiplication with less than 1% error, and CIFAR‐10 image classification with near‐software ...
Sangwook Youn, Hwiho Hwang, Hyungjin Kim
wiley   +1 more source

Low Power and Energy‐Efficient Design of MTJ/FinFET Circuits

open access: yesEngineering Reports, Volume 8, Issue 3, March 2026.
This work begins by outlining the fundamental concepts of MTJs, FinFETs, and the conventional hybrid CMOS/MTJ framework. It then explains the operating mechanism and configuration of the proposed STT‐MTJ/FinFET‐based OR logic gate. The final sections present the simulation outcomes and analyze the influence of FinFET fin variation.
Pillem Ramesh, Atul S. M. Tripathi
wiley   +1 more source

Research progress and challenges of the self-heating effect in STT-MRAM devices

open access: yesGongneng cailiao yu qijian xuebao
This paper present a systematic review of recent research progress and outstanding challenges related to the self-heating effect (SHE) in spin-transfer torque magnetic random-access memory (STT-MRAM) devices.
Zhangsheng LAN   +3 more
doaj   +1 more source

Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding

open access: yes, 2014
With attractive advantages like high density and low leakage, Spin-Transfer Torque Magnetoresistive RAM (STT-MRAM) is a promising candidate to replace conventional SRAM technology to build large-size and low-power on-chip caches.
Cong Xu   +7 more
core   +1 more source

Accuracy Improvement With Weight Mapping Strategy and Output Transformation for STT-MRAM-Based Computing-in-Memory

open access: yesIEEE Journal on Exploratory Solid-State Computational Devices and Circuits
This work presents an analog computing-in-memory (CiM) macro with spin-transfer torque magnetic random access memory (STT-MRAM) and 28-nm CMOS technology.
Xianggao Wang   +4 more
doaj   +1 more source

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