Results 71 to 80 of about 491 (183)

STT-DPSA: Digital PUF-Based Secure AuthenticationUsing STT-MRAM for the Internet of Things. [PDF]

Micromachines (Basel), 2020
Chien WC, Chang YC, Tsou YT, Kuo SY, Chang CR.   +4 more
europepmc   +1 more source

MRAM: A Versatile Non-Volatile Memory for Next-Generation Computing

Nanomaterials
Magnetoresistive random-access memory (MRAM), as a promising non-volatile memory technology, has attracted extensive research interest owing to its unique combination of high operating speed, exceptional endurance, low standby power consumption, and CMOS
Zhihan Wang, Haiwen Li, Sheng Jiang
doaj   +1 more source

Exploring the role of interfacial Dzyaloshinskii–Moriya interaction in write error rate anomalies of spin-transfer torque magnetic tunnel junctions

npj Spintronics
The performance and reliability of spin-transfer torque magnetic random-access memory (STT-MRAM) can be compromised by anomalous switching behavior, especially during high-speed operations.
Prosenjit Das, Md Mahadi Rajib, Jayasimha Atulasimha   +2 more
doaj   +1 more source

Controlling Bias Field of Pinned Layer Stacks for Double‐Pinned‐Layer Magnetic Tunnel Junction for STT‐MRAM

Advanced Electronic Materials
Double‐pinned‐layer Magnetic Tunnel Junction (Double PL MTJ) enhances spin‐transfer‐torque magneto‐resistive random‐access memory (STT‐MRAM) performance by requiring anti‐parallel magnetization between both PLs at free layer interfaces and minimizing ...
Shujun Ye, Koichi Nishioka
doaj   +1 more source

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

IEEE Access
In recent years, the rapid growth of big data and the increasing demand for high-performance computing have fueled the development of novel computing architectures.
Alaba Yusuf, Tosiron Adegbija, Dhruv Gajaria   +2 more
doaj   +1 more source

Enhanced write margin of perpendicular MRAM cells using thick MgO cap layer

AIP Advances
Implementation of spin transfer torque magneto-resistive random access memory (STT-MRAM) in memory chips requires that the write margin of the MRAM cell, defined as the difference between breakdown voltage and write voltage for the specified endurance ...
G. Mihajlović, T. S. Santos, J. Li, J. A. Katine, M. K. Grobis   +4 more
doaj   +1 more source

Novel CPU cache architecture based on two-dimensional MTJ device with ferromagnetic Fe3GeTe2

AIP Advances
With the development of Artificial Intelligence (AI) in recent years, the fields of computer, biology, medicine, and aerospace have demanded higher requirements for the processing and storage of information.
Shaopu Han, Yanfeng Jiang
doaj   +1 more source

Cryo-SIMPLY: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. [PDF]

Nanomaterials (Basel)
Moposita T, Garzón E, Teman A, Lanuzza M.   +3 more
europepmc   +1 more source

A generic compact model for resistive memories and switches. [PDF]

Sci Rep
Jung S, Kim H, Park J, Kim S, Kim MH.
europepmc   +1 more source

Research on Open Magnetic Shielding Packaging for STT and SOT-MRAM. [PDF]

Micromachines (Basel)
Ye H, Zhang X, Lu N, Li J, Jia J, Zhao G, Sun J, Zhang L, Wang C.   +8 more
europepmc   +1 more source