Results 51 to 60 of about 16,817 (212)

Multi-bit MRAM based high performance neuromorphic accelerator for image classification

Neuromorphic Computing and Engineering
Binary neural networks (BNNs) are the most efficient solution to bridge the design gap of the hardware implementation of neural networks in a resource-constrained environment.
Gaurav Verma, Sandeep Soni, Arshid Nisar, Brajesh Kumar Kaushik   +3 more
doaj   +1 more source

Magnetization dynamics at finite temperature in CoFeB–MgO based MTJs

Scientific Reports, 2023
The discovery of magnetization switching via spin transfer torque (STT) in PMA-based MTJs has led to the development of next-generation magnetic memory technology with high operating speed, low power consumption and high scalability.
Sutee Sampan-A-Pai, Rattaphon Phoomatna, Worawut Boonruesi, Andrea Meo, Jessada Chureemart, Richard F. L. Evans, Roy W. Chantrell, Phanwadee Chureemart   +7 more
doaj   +1 more source

Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

Advanced Intelligent Discovery, EarlyView.
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj, Ella Paasio, Sayani Majumdar   +2 more
wiley   +1 more source

A novel SRAM -STT-MRAM hybrid cache implementation improving cache performance

, 2017
International audienceMemories are currently a real bottleneck to design high speed and energy-efficient systems-on-chip. A significant increase of the performance gap between processors and memories is observed.
Coi, Odilia, Patrigeon, Guillaume, Senni, Sophiane, Sophiane Senni, Benoit, Pascal, Torres, Lionel, Odilia Coi, Pascal Benoit, Guillaume Patrigeon, Lionel Torres   +9 more
core   +1 more source

Exploiting Ferroelectric and Spintronic Dynamics for Neural Network Computation

Advanced Intelligent Systems, EarlyView.
Ferroelectric and spintronic devices, relying on the control of polarization and magnetization, offer intrinsically fast, durable, energy‐efficient, and low‐latency building blocks for analog in‐memory computing. The hysteretic dynamics of an order parameter are leveraged to provide nonvolatile, multistate memory and nonlinear switching. Brain‐inspired
Dashiell Harrison, Kevin Nadaud, Josquin Harrison, Guillaume F. Nataf, Laura Bégon‐Lours   +4 more
wiley   +1 more source

Research progresses on switching mechanism and advanced electrical characterizations of magnetic random access memory

Gongneng cailiao yu qijian xuebao
To address the energy efficiency and data throughput limitations of the Von Neumann architecture, computing-in-memory (CIM) systems based on spiking neural networks (SNNs) impose rigorous demands on the performance of non-volatile memory technologies ...
Xiaoqian MA, Shifan GAO, Yiming QU
doaj   +1 more source

Energy-efficient DSHE-MRAM-based in-memory computing for image segmentation [PDF]

APL Electronic Devices
Image segmentation approaches are among the crucial tasks in computer vision applications, such as object recognition, tracking, agriculture, autonomous vehicles, and medical imaging, relying heavily on deep learning neural networks (NN) for precise ...
Tanmoy Pramanik, Alok Kumar Shukla, Gaurav Verma, Amit Monga, Hemkant Nehete, Sandeep Soni   +5 more
doaj   +1 more source

Micromagnetic simulation of the temperature dependence of the switching energy barrier using string method assuming sidewall damages in perpendicular magnetized magnetic tunnel junctions

AIP Advances, 2020
The influence of magnetic damages at the sidewall of perpendicular magnetic tunnel junctions (p-MTJs), which are the core devices of spin-transfer-torque magnetoresistive random-access memory (STT-MRAM), is discussed based on the thermal stability factor,
Hiroshi Naganuma, Hideo Sato, Shoji Ikeda, Tetsuo Endoh   +3 more
doaj   +1 more source

On‐Chip Learning With Crossbar Arrays for Adaptive Edge Intelligence

Advanced Computing, Volume 1, Issue 1, December 2026.
Memristor crossbar arrays implemented on chip combines memory, computation, and learning. They allow for adapting the neural weights using the incoming sensor data. This architecture reduces data movement leading to low‐latency, energy‐efficient intelligence in edge while being reliability‐aware co‐design across devices, circuits, and algorithms that ...
Alex James
wiley   +1 more source

Modelling and Circuit Design for STT-MRAM [PDF]

, 2015
This thesis presents three research contributions in the areas of modelling, circuit-level design, and device-level design of spin-transfer-torque magnetoresistive random access memory (STT-MRAM).
Vatankhahghadim, Aynaz
core   +2 more sources