Results 41 to 50 of about 17,853 (211)
Design of a full 1Mb STT-MRAM based on advanced FDSOI technology
MATEC Web of Conferences, 2017 In one hand, the shrinking of CMOS technology nodes is dramatically increasing the leakage current in integrated circuits. In the other hand, modern portable devices first concern is power-efficiency to insure a better autonomy.
Jabeur Kotb, Prenat Guillaume
doaj +1 more source
Advanced Science, EarlyView.As CMOS technology approaches fundamental energy limits, new paradigms for low‐power information processing are required. Magnetic systems are attractive for their spin transport, yet current‐induced magnetization control is energy inefficient. Multiferroic heterostructures enable energy‐efficient electric field manipulation of magnetism.
Donghyeon Lee +3 more
wiley +1 more source
STT-MRAM Based NoC Buffer Design [PDF]
, 2012 As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design.
Vikram Kulkarni, Nikhil
core +2 more sources
STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications
, 2023 This work explores non-volatile (NV) embedded memories implemented by spin-transfer torque magnetic random access memories (STT-MRAMs). Our designs are based on state-of-the-art perpendicular magnetic tunnel junctions (MTJs) along with a commercial 65 nm
Esteban Garzon (16541610) +3 more
core +1 more source
Electrical TCAD Simulation of STT-MRAMs
2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)In this paper, we propose to develop a full TCAD simulation, using a commercial tool (Sentaurus), of an STT-MRAM device to better understand its electrical behavior. To our knowledge, it is the first time that a simulated I-V hysteresis loop is calibrated on experimental data.
Saifi, Hanane +8 more
openaire +2 more sources
Throughput-Efficient Network-on-Chip Router Design with STT-MRAM [PDF]
, 2013 As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck in large-scale multicore ...
Narayana, Sagar 1986-
core +1 more source
AIP Advances, 2020 In order to utilize perpendicular spin-torque-transfer magnetic-random-access-memory (p-STT MRAM) as a storage class memory, the achievement of performing multi-level-cell (MLC) operation is important in increasing the integration density of p-STT MRAM ...
Han-Sol Jun +7 more
doaj +1 more source
Reliability and performance evaluation for STT-MRAM under temperature variation
, 2016 International audienceSpin transfer torque magnetic random access memory (STT-MRAM) is a potential candidate for next generation universal memory technology, which possesses the high density and cost benefits of DRAM, the high access speed of SRAM, the ...
Zhang, Youguang +13 more
core +1 more source
Advanced Electronic Materials, EarlyView.In this work, low‐resolution infrared imaging is combined with a 28 nm FeFET IMC architecture to enable compact, energy‐efficient edge inference. MLC FeFET devices are experimentally characterized, and controlled multi‐level current accumulation is validated at crossbar array level.
Alptekin Vardar +9 more
wiley +1 more source
Embedded systems to high performance computing using STT-MRAM
, 2017 International audienceThe scaling limits of CMOS have pushed many researchers to explore alternative technologies for beyond CMOS circuits. In addition to the increased device variability and process complexity led by the continuous decreasing size of ...
Coi, Odilia +15 more
core +1 more source