Results 21 to 30 of about 16,817 (212)
STT-MRAM error correction technology based on LDPC coding
Spin transfer magnetoresistive random access memory (STT-MRAM) shows potential applications with the properties of non-volatility, low power consumption and high write/read speed.
Xue Zhang, Jianbin Liu, Yanfeng Jiang
doaj +1 more source
Screening of 193i and EUV lithography process options for STT-MRAM orthogonal array MTJ pillars
Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as the most promising candidate to replace the complementary metal-oxide-semiconductor (CMOS) based memories that are dominating the market in the last few decades.
Murat Pak +3 more
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WiSE : When Learning Assists Resolving STT-MRAM Efficiency Challenges
Spin Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising on-chip technologies, which delivers high density, non-volatility, and near-zero leakage power.
Beitollahi, Hakem, +5 more
core +1 more source
Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory
Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage ...
Luís Vitório Cargnini +4 more
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Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
As STT-MRAM mass production and deployment in industry is around the corner, high-quality yet cost-efficient manufacturing test solutions are crucial to ensure the required quality of products being shipped to end customers.
Wu, L. (author)
core +1 more source
The spin transfer torque magnetoresistive random access memory (STT-MRAM) is the leading candidate for spin-based memories. Nevertheless, the high write energy and read disturbance of the STT-MRAM motivated researchers to find other solutions.
Ibrahim Ahmed +5 more
doaj +1 more source
Novel multi-bit parallel pipeline-circuit design for STT-MRAM
In the paper, novel multi-bit parallel pipeline circuit design of STT-MRAM is proposed to improve the read and write efficiency. The shift register is utilized to change the series data into the parallel ones.
Guangjun Zhang, Yanfeng Jiang
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Hi-End: Hierarchical, Endurance-Aware STT-MRAM-Based Register File for Energy-Efficient GPUs
Modern Graphics Processing Units (GPUs) require large hardware resources for massive parallel thread executions. In particular, modern GPUs have a large register file composed of Static Random Access Memory (SRAM). Due to the high leakage current of SRAM,
Won Jeon +4 more
doaj +1 more source
The discovery of the giant magnetoresistance (GMR) effect in 1988 started a new field called spintronics and was recognized with the 2007 Nobel Prize in Physics, which was awarded to Fert and Grunberg.
M. Pinarbasi, A. D. Kent
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STT-MRAM Based NoC Buffer Design [PDF]
As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design.
Vikram Kulkarni, Nikhil
core +3 more sources

