Results 151 to 160 of about 3,273 (179)

Etching Methods for STT-MRAM

ECS Meeting Abstracts, 2017
Spin-transfer torque [1] MRAM (STT-MRAM) continues to be the subject of intense investigation due to its scalability and excellent endurance. Initially explored mainly as a DRAM replacement, STT-MRAM with perpendicularly magnetized materials is now targeted as a nonvolatile memory, medium-performance replacement for mobile applications, and more long
E. J. O'Sullivan, Anthony J Annunziata, Jemima Gonsalves, G. Hu, Eric A Joseph, Raman Kothandaraman, Gen Lauer, Nathan Marchack, J. J. Nowak, R. P. Robertazzi, J. Z. Sun, Thitima Suwannasiri, P. L. Trouilloud, Yu Zhu, D. C. Worledge   +14 more
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Exploiting STT-MRAM for approximate computing

2017 22nd IEEE European Test Symposium (ETS), 2017
Spin Transfer Torque Magnetic RAM (STT-MRAM) is an emerging non-volatile memory technology and a potential candidate to replace SRAM in processor caches. However, STT-MRAM suffers from a high write latency and high write energy consumption which have to be addressed for energy-efficient on-chip caches.
Sayed, Nour, Oboril, Fabian, Shirvanian, Azadeh, Bishnoi, Rajendra, Tahoori, Mehdi B.   +4 more
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Stochastic STT-MRAM Spiking Neuron Circuit

2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2020
We propose a compact STT-MRAM spiking neuron circuit that is a critical component of future hardware neural networks for accelerating deep learning. A SPICE compact model was established for the stochastic back-hopping oscillation of STT-MRAM, and the complete functionality of the spiking neuron circuit was demonstrated.
Fu-Xiang Liang, Paritosh Sahu, Ming-Hung Wu, Jeng-Hua Wei, Shyh-Shyuan Sheu, Tuo-Hung Hou   +5 more
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Improving Write Performance for STT-MRAM

IEEE Transactions on Magnetics, 2016
Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology.
Bishnoi, Rajendra, Ebrahimi, Mojtaba, Oboril, Fabian, Tahoori, Mehdi B.   +3 more
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Low power computing using STT-MRAM

2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS), 2014
The computing systems are scaling down 100 times every decade, while the processing power doubles every two years. As a result, the power density has been the one of the most critical issues that limit the modern processors. Therefore, new technologies and computer architectures are under tensed development to reduce the power consumption.
Kejie Huang, Rong Zhao
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STT-MRAM for low power systems

2015 International Symposium on VLSI Technology, Systems and Applications, 2015
Recently in semiconductor memories, it is becoming difficult to meet the target performance requirements by technology development based solely on device scaling. Especially, due to the increase in memory capacity, increased operation speed and increased leakage current of MOSFET, the power consumption of LSI is rapidly increasing.
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Security primitives (PUF and TRNG) with STT-MRAM

2016 IEEE 34th VLSI Test Symposium (VTS), 2016
The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency ...
Vatajelu, Elena Ioana, Di Natale, Giorgio, Prinetto, Paolo   +2 more
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Survey of STT-MRAM Cell Design Strategies

ACM Journal on Emerging Technologies in Computing Systems, 2017
Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated ...
Soheil Salehi, Deliang Fan, Ronald F. Demara   +2 more
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Implementation of FinFET based STT-MRAM bitcell

2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies, 2014
DGMOSFET or FinFET has emerged as a promising candidate to replace conventional MOSFET which suffers from various disadvantages like subthreshold leakage, gate-dielectric leakage, SCE (short-channel effect) or DIBL (drain-induced barrier lowering). Emerging technology like FinFET reduces these and improves variability.
Arundhati Bhattacharya, Soumitra Pal, Aminul Islam   +2 more
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Readability challenges in deeply scaled STT-MRAM

2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS), 2014
Spin transfer torque magnetic random access memory (STT-MRAM) is currently under intensive investigation for one of the possible alternatives to extend the Moore's Law beyond the CMOS technology scaling limit. Its advantageous features, such as nonvolatility, high speed, low power and excellent scalability etc, attract worldwide RD and then we present ...
Wang Kang, Yuanqing Cheng, Youguang Zhang, Dafine Ravelosona, Weisheng Zhao   +4 more
openaire   +1 more source