Results 141 to 150 of about 491 (183)

STT MRAM patterning challenges

SPIE Proceedings, 2013
In this paper we report on the patterning challenges for the integration of Spin-Transfer Torque Magneto-Resistive- Random-Access Memory (STT MRAM). An overview of the different patterning approaches that have been evaluated in the past decade is presented.
Werner Boullart, Dunja Radisic, Vasile Paraschiv, Sven Cornelissen, Mauricio Manfrini, Koichi Yatsuda, Eiichi Nishimura, Tetsuya Ohishi, Shigeru Tahara   +8 more
openaire   +1 more source

Write-optimized reliable design of STT MRAM

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, 2012
Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is still a major challenge. As a result, the optimization of the memory for write is critical.In this work,
Yusung Kim 0002, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy 0001   +4 more
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Test challenges in embedded STT-MRAM arrays

2017 18th International Symposium on Quality Electronic Design (ISQED), 2017
Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging memory technology which exhibits non-volatility, high density and nanosecond read and write times. These attributes of STT-MRAM make it suitable for last level embedded caches.
Insik Yoon, Arijit Raychowdhury
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FPGA Implementation of A Hybrid Decoder for STT-MRAM

2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018
Process variation and random thermal fluctuation severely affect the reliability of spin-torque transfer magnetic random access memory (STT-MRAM). This paper presents an FPGA-based two-stage hybrid decoder of extended Hamming codes for STT-MRAM with less decoding latency and lower implementation complexity.
Xue Liu, Kui Cai 0001, Zhen Mei 0001
openaire   +1 more source

STT-MRAM for Embedded Memory Applications

2020 IEEE International Memory Workshop (IMW), 2020
With traditional embedded memories, such as eFlash and SRAM, facing major challenge of scaling beyond 28 nm, STT-MRAM stands out from competing emerging NVM technologies as the preferred technology for both embedded flash and SRAM replacements. Having high data retention, reflow compatibility and high endurance, MRAM is ready for production to replace ...
Zihui Wang, Xiaojie Hao, Pengfa Xu, Longqian Hu, Dongha Jung, Woojin Kim, Kimihiro Satoh, Bing Yen, Zhiqiang Wei, Lienchang Wang, Jing Zhang, Yiming Huai   +11 more
openaire   +1 more source

Opportunistic write for fast and reliable STT-MRAM

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017
Due to the stochastic switching behavior of the bit-cell in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), an excessive write margin is required to guarantee an acceptable level of reliability and yield. This prevents the usage of STT-MRAM in fast memories such as L1 or L2 caches. The excessive write margin of STT-MRAM can be reduced to
Sayed, N., Ebrahimi, M., Bishnoi, R., Tahoori, M. B.   +3 more
openaire   +2 more sources

Read disturbance issue for nanoscale STT-MRAM

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA), 2015
Spin transfer torque magnetic random access memory (STT-MRAM) has been widely considered as one of the most promising candidates for the next-generation nonvolatile memory technologies, thanks to its attractive features, including high density, high speed, low power and high endurance etc.
Yi Ran, Wang Kang 0001, Youguang Zhang, Jacques-Olivier Klein, Weisheng Zhao 0001   +4 more
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28nm STT-MRAM Array and Sense Amplifier

2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2019
Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a replacement for currently used embedded non-volatile memory. We describe the characteristics of STT-MRAM and explore aspects of the memory array including trade-off in size, switching, read speed, temperature effects, layout, and power consumption.
Jin Woong Kwak, Andrew Marshall, Harvey Stiegler   +2 more
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STT-MRAM - Status and Outlook

2022 IEEE 33rd Magnetic Recording Conference (TMRC), 2022
D. C. Worledge, C. Safranski, G. Hu, J. Z. Sun, P. Hashemi, S. L. Brown, L. Buzi, C. P. D'Emic, M. G. Gottwald, O. Gunawan, H. Jung, S. Karimeddiny, J. Kim, P. L. Trouilloud   +13 more
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Progress and outlook for STT-MRAM

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011
Yiming Huai, Yuchen Zhou, Ioan Tudosa, Roger Malmhall, Rajiv Ranjan, Jing Zhang   +5 more
openaire   +1 more source