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Magnetic Shielding and Packaging of STT MRAM
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC), 2018A magnetic shield was developed for the standard BGA MRAM DDRS chip to increase the magnetic interference tolerance from 100}}oe to more than 500 oetextbf{{. This enabled the low power and fast speed MRAM devices to operate in more rugged conditions. The shield used a soft ferromagnetic material to provide the passive shielding.
Lim Teck Guan +6 more
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Progress and outlook for STT-MRAM
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011Yiming Huai +5 more
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Electromagnetic Characteriation of STT-MRAM
2023 IEEE 7th International Symposium on Electromagnetic Compatibility (ISEMC), 2023Yiming Zhang +5 more
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ROCKY: A Robust Hybrid On-Chip Memory Kit for the Processors With STT-MRAM Cache Technology
IEEE Transactions on Computers, 2021Amir Mahdi Hosseini Monazzah +1 more
exaly
Layout-aware optimization of stt mrams
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012Sumeet Kumar Gupta +3 more
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Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021Mehdi Sadi, Kaniz Mishty
exaly
Hard Error Correction in STT-MRAM
2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)Surendra Hemaram +5 more
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Temperature Increase in STT-MRAM at Writing: A Fully Three-Dimensional Finite Element Approach
Solid-State Electronics, 2022Siegfried Selberherr +2 more
exaly
A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches
IEEE Transactions on Reliability, 2020Hossein Asadi +2 more
exaly