Results 191 to 200 of about 12,742 (221)

Opportunistic write for fast and reliable STT-MRAM

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017
Due to the stochastic switching behavior of the bit-cell in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), an excessive write margin is required to guarantee an acceptable level of reliability and yield. This prevents the usage of STT-MRAM in fast memories such as L1 or L2 caches. The excessive write margin of STT-MRAM can be reduced to
Sayed, N., Ebrahimi, M., Bishnoi, R., Tahoori, M. B.   +3 more
openaire   +2 more sources

Status and outlook of STT-MRAM development

SPIE Proceedings, 2014
MTJ stack is optimized for TMR at low RA region, high PMA and 400oC post annealing capability. Atomic level smooth bottom electrode with 0.5A roughness was developed and positive effects on annealing capability and PMA was demonstrated. The scaling challenge of STT-MRAM read operation down to sub-10nm is discussed.
T. Min, G. S. Kar, J. Swerts, S. Mertens, S. Coseman, J. Bekaert, K. Xu, L. Souriau, D. Radisic, H. Okuyama, K. Nishimura, T. Seino, K. Tsunekawa   +12 more
openaire   +1 more source

Improving Write Performance for STT-MRAM

IEEE Transactions on Magnetics, 2016
Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology.
Bishnoi, Rajendra, Ebrahimi, Mojtaba, Oboril, Fabian, Tahoori, Mehdi B.   +3 more
openaire   +2 more sources

Magnetic Shielding and Packaging of STT MRAM

2018 IEEE 20th Electronics Packaging Technology Conference (EPTC), 2018
A magnetic shield was developed for the standard BGA MRAM DDRS chip to increase the magnetic interference tolerance from 100}}oe to more than 500 oetextbf{{. This enabled the low power and fast speed MRAM devices to operate in more rugged conditions. The shield used a soft ferromagnetic material to provide the passive shielding.
Lim Teck Guan, Eva Wai Leong Ching, Lim Wei Yi, Ta-Chien Cheng, Kangho Lee, Jason Janesky, Earl Gow   +6 more
openaire   +1 more source

STT-MRAM - Status and Outlook

2022 IEEE 33rd Magnetic Recording Conference (TMRC), 2022
D. C. Worledge, C. Safranski, G. Hu, J. Z. Sun, P. Hashemi, S. L. Brown, L. Buzi, C. P. D'Emic, M. G. Gottwald, O. Gunawan, H. Jung, S. Karimeddiny, J. Kim, P. L. Trouilloud   +13 more
openaire   +1 more source

Progress and outlook for STT-MRAM

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011
Yiming Huai, Yuchen Zhou, Ioan Tudosa, Roger Malmhall, Rajiv Ranjan, Jing Zhang   +5 more
openaire   +1 more source

Electromagnetic Characteriation of STT-MRAM

2023 IEEE 7th International Symposium on Electromagnetic Compatibility (ISEMC), 2023
Yiming Zhang, Zhenbin Gao, Jianfei Wu, Yanfang Lu, Yang Li, Hongli Zhang   +5 more
openaire   +1 more source

STT-MRAM for low power systems

2015 International Symposium on VLSI Technology, Systems and Applications, 2015
Recently in semiconductor memories, it is becoming difficult to meet the target performance requirements by technology development based solely on device scaling. Especially, due to the increase in memory capacity, increased operation speed and increased leakage current of MOSFET, the power consumption of LSI is rapidly increasing.
openaire   +1 more source

Layout-aware optimization of stt mrams

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Sumeet Kumar Gupta, Sang Phill Park, Niladri Narayan Mojumder, Kaushik Roy 0001   +3 more
openaire   +1 more source

Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021
Mehdi Sadi
exaly