Results 191 to 200 of about 17,853 (211)

Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

IEEE Transactions on Electron Devices, 2015
Weisheng Zhao, Liuyang Zhang, Wang Kang
exaly  

Review of STT-MRAM Circuit Design Strategies, and a 40-Nm 1T-1MTJ 128Mb STT-MRAM Design Practice

2020
Hiroaki Honjo, Mitsuo Yasuhira, Toru Yoshiduka   +2 more
exaly  

Complimentary Polarizers STT-MRAM (CPSTT) for On-Chip Caches

IEEE Electron Device Letters, 2013
Xuanyao Fong, Kaushik Roy
exaly  

Recent Progresses in STT-MRAM and SOT-MRAM for Next Generation MRAM

2020
Ikeda Shoji, Koichi Nishioka, Tetsuo Endoh   +2 more
exaly  

Fast Cacheline-Based Data Replacement for Hybrid DRAM and STT-MRAM Main Memory

IEICE Electronics Express, 2020
Mao Ni
exaly  

Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
Eby Friedman, Engin İpek, Ravi Patel
exaly  

STT-MRAM cell structures

2015
LIU JUN, SANDHU GURTEJ
openaire   +3 more sources

R-MRAM: A ROM-Embedded STT MRAM Cache

IEEE Electron Device Letters, 2013
Xuanyao Fong, Kaushik Roy, Dongsoo Lee
exaly  

Read Disturbance Issue and Design Techniques for Nanoscale STT-MRAM

Journal of Systems Architecture, 2016
Weisheng Zhao, Yi Ran, Wang Kang
exaly  

Design-for-Test for Intermittent Faults in STT-MRAMs

2024 IEEE European Test Symposium (ETS)
Sicong Yuan, Mohammad Amin Yaldagard, Hanzhi Xun, Moritz Fieback, Erik Jan Marinissen, Woojin Kim, Siddharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui   +9 more
openaire   +1 more source