Results 211 to 220 of about 12,742 (221)
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Read disturbance issue and design techniques for nanoscale STT-MRAM
Journal of Systems Architecture, 2016Yi Ran, Wang Kang, Youguang Zhang
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Life-time degradation of STT-MRAM by self-heating effect with TDDB model
Solid-State Electronics, 2020Guangjun Zhang +2 more
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Review of STT-MRAM circuit design strategies, and a 40-nm 1T-1MTJ 128Mb STT-MRAM design practice
2020Mitsuo Yasuhira, Hiroaki Honjo
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A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012Jisu Kim, Kyungho Ryu, Seung H Kang
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Write energy reduction of STT-MRAM based multi-core cache hierarchies
International Journal of Electronics Letters, 2019Yogendra Gupta, Lava Bhargava
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Write-Optimized STT-MRAM Bit-Cells Using Asymmetrically Doped Transistors
IEEE Electron Device Letters, 2014Sri Harsha Choday +2 more
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Overview of Reliability in Scaling Embedded STT-MRAM
2025 IEEE International Reliability Physics Symposium (IRPS)Hyunsung Jung +4 more
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Design-for-Test for Intermittent Faults in STT-MRAMs
2024 IEEE European Test Symposium (ETS)Sicong Yuan +9 more
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Asymmetric and Adaptive Error Correction in STT-MRAM
IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsSurendra Hemaram +7 more
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DTCO for Fast STT-MRAM Periphery Operation
2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)Ahmed Hossam-Eldeen +4 more
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