Results 1 to 10 of about 401 (157)
A Timing-Based Split-Path Sensing Circuit for STT-MRAM [PDF]
Micromachines, 2022 Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM ...
Bayartulga Ishdorj +3 more
doaj +2 more sources
L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime. [PDF]
PLoS ONE, 2023 Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the ...
Carlos Escuin +5 more
doaj +2 more sources
Binary-Weighted Neural Networks Using FeRAM Array for Low-Power AI Computing [PDF]
NanomaterialsArtificial intelligence (AI) has become ubiquitous in modern computing systems, from high-performance data centers to resource-constrained edge devices.
Seung-Myeong Cho +5 more
doaj +2 more sources
EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit
IEEE Access, 2022 Spin Transfer Torque Random Access Memory (STT-RAM) has garnered interest due to its various characteristics such as non-volatility, low leakage power, high density.
Saeed Seyedfaraji +3 more
doaj +1 more source
IEEE Access, 2023 In non-volatile random-access memory (RAM) technologies, the spin-torque transfer magnetic random-access memory (STT-MRAM) is a promising candidate. STT-MRAM has attracted attention owing to its advantages, such as a high density, high endurance, and ...
Thien An Nguyen, Jaejin Lee
doaj +1 more source
Reuse Detector: Improving the Management of STT-RAM SLLCs [PDF]
The Computer Journal, 2017 Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the prime contender due to its better energy efficiency, smaller die footprint and higher scalability.
Roberto Rodríguez-Rodríguez +10 more
openaire +6 more sources
IEEE Access, 2020 In Cyber-Physical-Social Systems (CPSS), large-scale data are continually generated from edge computing devices in our daily lives. These heterogeneous data collected from CPSS are urgently needed to be processed efficiently with low power consumption ...
Fanfan Shen, Chao Xu, Jun Zhang
doaj +1 more source
STT-BSNN: An In-Memory Deep Binary Spiking Neural Network Based on STT-MRAM
IEEE Access, 2021 This paper proposes an in-memory binary spiking neural network (BSNN) based on spin-transfer-torque magnetoresistive RAM (STT-MRAM). We propose residual BSNN learning using a surrogate gradient that shortens the time steps in the BSNN while maintaining ...
Van-Tinh Nguyen +3 more
doaj +1 more source
High Bandwidth and Highly Available Packet Buffer Design Using Multi-Retention Time MRAM
IEEE Access, 2023 Significant challenges are posed in the design of routers and switches by the explosive growth of internet traffic and the stringent requirements for high availability in the research area of computer networks.
Yongwoon Song, Munhyung Lee, Hyukjun Lee
doaj +1 more source
On the Design of 7/9-Rate Sparse Code for Spin-Torque Transfer Magnetic Random Access Memory
IEEE Access, 2021 A design of 7/9-rate sparse code for spin-torque transfer magnetic random access memory (STT-MRAM) is proposed in this work. The STT-MRAM using spin-polarized current through magnetic tunnel junction (MTJ) to write data is one of the most promising ...
Chi Dinh Nguyen
doaj +1 more source