Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization
IEEE Access, 2018 As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from last level cache (LLC), which are frequently repeated, has become a major concern.
Navid Khoshavi, Ronald F. Demara
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HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems [PDF]
IEEE Transactions on Computers, 2019 Kyle Kuan, Tosiron Adegbija
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A statistical STT-RAM retention model for fast memory subsystem designs
, 2017 Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory (NVM) solution to implement on-chip caches and off-chip main memories for its high integration density and short access time, but it suffers from considerable write ...
Liu, Zihao +9 more
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Circuit and Architecture Co-Design of STT-RAM for High Performance and Low Energy [PDF]
, 2017 Spin-Transfer Torque Random Access Memory (STT-RAM) has been proved a promising emerging nonvolatile memory technology suitable for many applications such as cache mem- ory of CPU.
Bi, Xiuyuan
core +1 more source
NVSim-VXs: An improved NVSim for variation aware STT-RAM simulation
2016 Seventh International Green and Sustainable Computing Conference (IGSC), 2016 Spin-transfer torque random access memory (STT-RAM) recently received significant attentions for its promising characteristics in cache and memory applications.
Wujie Wen +13 more
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An Adaptive ECC Scheme for Runtime Write Failure Suppression of STT-RAM Cache [PDF]
, 2016 Spin-transfer torque random access memory (STT-RAM) features many attractive charac- teristics, including near-zero standby power, nanosecond access time, small footprint, etc.
Wang, Xue
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Reverse Connection of MTJ Device in STT-RAM Cell [PDF]
, 2013 STT-RAM technology is an emerging memory technology which is a future replacement for conventional memory technologies. STT-RAM promises fast read-write-access speeds, low power consumption, high density, non-volatility and very long life time.
Bayram, Ismail
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Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Computer Architecture News, 2011 Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-core architectures.
Asit K Mishra +2 more
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Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM
IEEE Transactions on Reliability, 2016 Bi Wu, Yuanqing Cheng, Jianlei Yang
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Promoting MLC STT-RAM for the Future Persistent Memory System
2017 IEEE 15th Intl Conf on Dependable, Autonomic and Secure Computing, 15th Intl Conf on Pervasive Intelligence and Computing, 3rd Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress(DASC/PiCom/DataCom/CyberSciTech), 2017 As the memory wall issue continues in the era of big data, researchers have been exploring emerging technologies to replace or complement the current DRAM based main memory system. Among them, Multi-Level Cell (MLC) configurations of Spin-Transfer Torque Random Access Memory (STT-RAM) attracts tremendous interests and has been deployed as the onchip ...
Xunchao Chen, Jun Wang, Jian Zhou
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