Results 31 to 40 of about 168,024 (182)

People Counting and Positioning Using Low‐Resolution Infrared Images for FeFET‐Based In‐Memory Computing

open access: yesAdvanced Electronic Materials, EarlyView.
In this work, low‐resolution infrared imaging is combined with a 28 nm FeFET IMC architecture to enable compact, energy‐efficient edge inference. MLC FeFET devices are experimentally characterized, and controlled multi‐level current accumulation is validated at crossbar array level.
Alptekin Vardar   +9 more
wiley   +1 more source

SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning [PDF]

open access: yes
Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM\u27s write energy and latency.
Gajaria, Dhruv   +2 more
core   +1 more source

Low Power Design for Future Wearable and Implantable Devices

open access: yesJournal of Low Power Electronics and Applications, 2016
With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications.
Katrine Lundager   +4 more
doaj   +1 more source

Silicon Nitride Resistive Memories

open access: yesAdvanced Electronic Materials, EarlyView.
Amorphous SiNx is an attractive resistance switching material for ReRAM applications due to its physicochemical properties, such as humidity resistance, low oxygen diffusivity, and is used as a metal diffusion blocker. By modifying the ratio between N and Si atoms, the microstructure of the SiNx is affected, rendering it possible to change the ...
Alexandros‐Eleftherios Mavropoulis   +7 more
wiley   +1 more source

PS3-RAM: A fast portable and scalable statistical STT-RAM reliability/energy analysis method

open access: yes, 2014
The development of emerging spin-transfer torque random access memory (STT-RAM) is facing two major technical challenges-poor write reliability and high write energy, both of which are severely impacted by process variations and thermal fluctuations. The
Wen, Wujie   +4 more
core   +1 more source

낮은 에너지 소비 및 성능 오버헤드를위한 안정적인 Spin-Transfer Torque RAM (STT-RAM) 캐시

open access: yes, 2020
학위논문(박사) - 한국과학기술원 : 전산학부, 2020.2,[v, 75 p. :]The demand for the increased memory size in the computer industry and the scalability challenges of the traditional memory technologies inspired the researches towards next-generation memory technologies.
Qureshi, Muhammad Avais
core   +1 more source

Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

open access: yesAdvanced Intelligent Discovery, EarlyView.
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj   +2 more
wiley   +1 more source

Headless Compression Screw Fixation Alone for Lunate Coronal Fractures in Kienböck Disease

open access: yesOrthopaedic Surgery, EarlyView.
The optimal management of Kienböck disease with lunate coronal fractures remains controversial. Previous studies advocated excision of the fractured lunate followed by scaphotrapeziotrapezoidal (STT) fusion or proximal row carpectomy. In this study, headless compression screw alone achieved fracture healing and satisfactory clinical outcomes in ...
Jiangchao Zhang   +4 more
wiley   +1 more source

STT-HDC: An Efficient Time-Domain In-Memory Hyper-Dimensional Computing Design Based on STT-MRAM

open access: yesIEEE Access
This paper presents an efficient in-memory hyperdimensional computing (HDC) design based on spin transfer-torque magnetoresistive RAM (STT-MRAM), named STT-HDC. A novel time-domain sense amplifier circuit is proposed that significantly simplifies Hamming
Thi-Nhan Pham   +3 more
doaj   +1 more source

On‐Chip Learning With Crossbar Arrays for Adaptive Edge Intelligence

open access: yesAdvanced Computing, Volume 1, Issue 1, December 2026.
Memristor crossbar arrays implemented on chip combines memory, computation, and learning. They allow for adapting the neural weights using the incoming sensor data. This architecture reduces data movement leading to low‐latency, energy‐efficient intelligence in edge while being reliability‐aware co‐design across devices, circuits, and algorithms that ...
Alex James
wiley   +1 more source

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