Results 141 to 150 of about 1,678 (162)

Energy reduction for STT-RAM using early write termination

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too
Ping Zhou, Bo Zhao, Jun Yang, Youtao Zhang   +3 more
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STT-RAM based energy-efficiency hybrid cache for CMPs

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Modern high performance Chip Multiprocessor (CMP) systems rely on large on-chip cache hierarchy. As technology scales down, the leakage power of present SRAM based cache gradually dominates the on-chip power consumption, which can severely jeopardize system performance.
Jianhua Li, Chun Jason Xue, null Yinlong Xu   +2 more
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TENDRA: Targeted Endurance Attack on STT-RAM LLC

IEEE Embedded Systems Letters
Spin Transfer Torque RAM (STT-RAM) based Last Level Cache (LLC) offers significant benefits like high density and low refresh energy, but faces challenges like high write latency and limited endurance. Malicious attacks in a multi-core setup need access to only a single core to perform repeated attacks on specific memory locations that can lead to an ...
Prabuddha Sinha, Mangena Likhit Sai, Shirshendu Das, Venkata Kalyan Tavva   +3 more
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Write-Amount-Aware Management Policies for STT-RAM Caches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
Spin-transfer torque random access memory (STT-RAM) technology has emerged as one of the most promising memory technologies owing to its nonvolatility, high density, and low-leakage power characteristics. However, STT-RAM has certain drawbacks such as high write energy consumption and limits to the number of write cycles.
Hyeonggyu Kim, Soontae Kim, Jooheung Lee
openaire   +1 more source

Lower-bits cache for low power STT-RAM caches

2012 IEEE International Symposium on Circuits and Systems, 2012
As power-efficient design becomes more important, spin-transfer torque RAM (STT-RAM) has drawn a lot of attention due to its ability to meet both high performance and low power consumption. However, its high write energy incurs an increase of dynamic power consumption and may offset power saving due to its low static power.
Junwhan Ahn, Kiyoung Choi
openaire   +1 more source

Enhancing the Lifetime of STT-RAM by IFTRP

Engineering Research Express
Abstract Spin Transfer Torque Random Access memory (STT-RAM) is a better alternative to overcome the shortcomings of the existing memory technologies. But, the implementation of STT-RAM memory technologies on the existing memory are limited due to its write restriction.
Bhukya Krishna Priya, Bhukya Krishna Naick, N Ramasubramanian   +2 more
openaire   +1 more source

A Restore-Free Mode for MLC STT-RAM Caches

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019
Spin-transfer torque RAM (STT-RAM) caches are foreseen to replace traditional static RAM caches because of their nonvolatile nature and high density. Multilevel cell (MLC) STT-RAMs further enhance the storage density of single-level cell STT-RAMs. However, the two-step read/write process in MLC STT-RAMs adversely affects performance, energy consumption,
Muhammad Avais Qureshi, Hyeonggyu Kim, Soontae Kim   +2 more
openaire   +1 more source

STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future nonvolatile memories. It advantages the benefits of current state-of-the-art memories including high-speed read operation (of static RAM), high density (of dynamic RAM), and nonvolatility (of flash memories). However, the write operation in the 1T-1MTJ
Hooman Farkhani, Mohammad Tohidi, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi   +4 more
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Ion Beam Patterning of High-Density STT-RAM Devices

IEEE Transactions on Magnetics, 2017
Dependence on ion beam energy, ion species, and incidence angles is investigated to reduce sidewall re-deposition on the magnetic tunnel junction barrier. Experimental and simulated etch data, for a representative spin-torque transfer random access memory structure with 40 nm critical dimension and 150 nm pitch, indicated a reduction in the sidewall re-
Vincent Ip, Shuogang Huang, Santino D. Carnevale, Ivan L. Berry, Katrina Rook, Thorsten B. Lill, Ajit P. Paranjpe, Frank Cerio   +7 more
openaire   +1 more source

A dual-mode architecture for fast-switching STT-RAM

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, 2012
In the past, the spin-transfer torque RAM (STT-RAM) suffered from the slow write speed and the high write energy consumption. The latest progress in device engineering has dramatically reduced the write time to a few nanoseconds and hence enabled the fast-switching STT-RAM (FS-STT-RAM).
Zhenyu Sun, Hai Li, Wenqing Wu
openaire   +1 more source