Results 91 to 100 of about 361,658 (190)

Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening

, 2019
In the standard MOSFET description of the drain current I D as a function of applied gate voltage V GS, the subthreshold swing SS(T)≡ dV GS/d log I D has a fundamental lower limit as a function of temperature T given by SS(T)= ln 10 k B T/e.
Jansen, Louis, Barral, V., Billiot, G., Bertrand, B., Galy, Philippe, Cassé, Mikaël, Vinet, M., Bohuslavskyi, Heorhii; id_orcid, jehl, xavier, Pillonnet, Gaël, Sanquer, M., Arnaud, F., Guevel, Loïck Le, Hutin, Louis, Sylvain, BARRAUD, Franceschi, S. De   +15 more
core   +1 more source

A Co‐Designed Implicit‐Reset Path PFD and Current Mismatch Compensated CP Enabling Sub‐0.5% Mismatch and Dead Zone‐Free for Low‐Spur PLLs

International Journal of Circuit Theory and Applications, EarlyView.
A co‐designed implicit‐reset phase‐frequency detector (PFD) and nonlinear amplifier‐assisted charge pump (CP) achieve dead zone‐free operation from 10 MHz to 4.7 GHz with < 0.5% current mismatch without calibration, enabling −80 dBc of reference spur and 0.50 ps of RMS jitter in a 180 nm of CMOS PLL.
A. Ghaemnia, Jincheng Yang, Xiaojiong Fei, G. Zhang   +3 more
wiley   +1 more source

Entrainer selection for pressure swing batch distillation [PDF]

, 2008
The feasibility of the separation of binary homoazeotropes with pressure swing batch distillation by the application of an entrainer is studied. The feasibility studies are based on the assumption of maximal separation and on the analysis of batch ...
Láng, Péter, Modla, Gábor, Kopasz, Árpád   +2 more
core   +1 more source

Subthreshold Time‐Mode All‐Digital DLL With Built‐In Linearization

International Journal of Circuit Theory and Applications, EarlyView.
This paper presents a subthreshold time‐mode all‐digital delay‐locked loop (DLL) for low‐frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. Phase error is processed by a time‐mode proportional block (
Fei Yuan, Wenhao Wu, Yushi Zhou
wiley   +1 more source

Effect of Gate Length Scaling on Various Performance Parameters in DG-FinFETs: a Simulation Study [PDF]

Журнал нано- та електронної фізики, 2012
This paper presents a simulation study on the gate length scaling of a double gate (DG) FinFET. To achieve channel lengths smaller than 20 nm, innovative device architectures will be necessary to continue the benefits previously acquired through scaling.
Rakesh Vaid, Meenakshi Chandel
doaj  

Improving Analog Performance and Suppression of Subthreshold Swing using Hetero Junction Less Double Gate Tunnel FETs

, 2017
In this paper, we investigated a new device, Hetero junction less H JL Double Gate Tunnel Field Effect Transistors DGTFET with high k. III V semiconductor material like InAs Si gives excellent performance when InAs uses at source side, because of low ...
Dr. Prabha Shreeraj Nair
core   +1 more source

Low‐Dimensional Materials and Van Der Waals Heterostructures for Energy Application: A Comprehensive Review

ENERGY &ENVIRONMENTAL MATERIALS, EarlyView.
Low‐dimensional materials (0D, 1D, and 2D) exhibit unique electronic and physicochemical properties, enabling advanced nanoelectronic and optoelectronic devices. Mixed‐dimensional heterostructures combine these materials to enhance functionality.
Qaisar Alam, Sajjad Ali, Pir Muhammad Ismail, ABM Sharif Hossain   +3 more
wiley   +1 more source

Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors

IEEE Journal of the Electron Devices Society, 2019
Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure.
Meng-Ju Tsai, Kang-Hui Peng, Chong-Jhe Sun, Siao-Cheng Yan, Chieng-Chung Hsu, Yu-Ru Lin, Yu-Hsien Lin, Yung-Chun Wu   +7 more
doaj   +1 more source

Material design strategies for flexible n‐type polymer semiconductors

FlexMat, EarlyView.
This Perspective surveys recent progress in flexible n‐type polymer semiconductors, emphasizing the interplay between molecular design and microstructure control. It outlines strategies including backbone and side‐chain engineering, multilevel microstructure optimization, to maintain charge‐transport pathways under mechanical deformation.
Xiao‐Yan Zhang, Yang‐Yang Zhou, Jie‐Yu Wang, Jian Pei, Ze‐Fan Yao   +4 more
wiley   +1 more source

Semi-analytical Model for the Estimation of the Subthreshold Swing in Dirac-Source FETs

A 2D analytical model for the potential profile in the semiconductor channel of two-dimensional (2D) Dirac-Source (DS) FETs is worked out and compared with a rigorous numerical solution of Poisson’s equation.
Gnani E., Baccarani G., Ugolini T.
core   +1 more source