Results 11 to 20 of about 6,570 (171)

Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10

Jurnal Elkomika, 2022
ABSTRAK Desain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan.
MUHAMMAD ULIN NUHA, HARI ARIEF DHARMAWAN, SETYAWAN PURNOMO SAKTI   +2 more
doaj   +1 more source

Fully passive noise‐shaping successive approximation register analog‐to‐digital converter realizing 2 × gain without capacitor stacking

Electronics Letters, 2023
The fully passive noise shaping (NS) successive approximation register (SAR) analog‐to‐digital converters (ADCs) are simple, operational transconductance amplifier (OTA) free and scaling friendly. Previous passive NS‐SAR ADCs rely on the multi‐path‐input
Xingshuai Zou, Jiaxin Liu, Qiang Li
doaj   +1 more source

A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET

IEEE Access, 2021
This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system.
Yan Zheng, Jingchao Lan, Fan Ye, Junyan Ren   +3 more
doaj   +1 more source

Implementation of a digital trim scheme for SAR ADCs [PDF]

Advances in Radio Science, 2013
Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975).
J. Bialek, A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, T. Ussmueller   +5 more
doaj   +1 more source

A low‐power and area‐efficient ultrasound receiver using beamforming successive approximation register analog‐to‐digital converter with capacitive digital‐to‐analog converter combined delay cell structure for 3‐D imaging systems

Electronics Letters, 2022
The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver,
Seungah Lee, Soohyun Yun, Joonsung Bae
doaj   +1 more source

Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC [PDF]

, 2017
This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application.
Cen, Yuanjun, Fan, Hua, Heidari, Hadi, Hu, Daqian, Li, Dagang, Maloberti, Franco   +5 more
core   +1 more source

A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

IEEE Access, 2023
This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over
Hyeonsik Kim, Soohoon Lee, Jintae Kim
doaj   +1 more source

High-Resolution ADCs Design in Image Sensors [PDF]

, 2018
This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-ifications such as Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and ...
Cen, Yuanjun, Fan, Hua, Feng, Quanyuan, Heidari, Hadi, Hu, Daqian, Li, Dagang, Maloberti, Franco, Yang, Jingxuan   +7 more
core   +1 more source

A passive second‐order noise‐shaping SAR ADC architecture with increased freedom in NTF synthesis and relaxed clock‐jitter issue

Electronics Letters, 2022
Noise‐shaping (NS) successive approximation register (SAR) analogue‐to‐digital converters (ADCs) are an attractive architecture for power and area efficiency in moderate resolution and bandwidth applications.
Weihao Wang, Xiao Wang, Bo Zhao, Kong‐pang Pun   +3 more
doaj   +1 more source

A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology [PDF]

Journal of Electrical and Computer Engineering Innovations, 2017
A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper.
S. Mahdavi
doaj   +1 more source