Results 21 to 30 of about 6,570 (171)
High Linearity SAR ADC for Smart Sensor Applications [PDF]
, 2018 This paper presents capacitive array optimization technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor ...
Cen, Yuanjun +7 more
core +1 more source
Two‐step, piecewise‐linear SAR ADC with programmable transfer function
Electronics Letters, 2019 A 7‐bit successive approximation register (SAR) analogue‐to‐digital converter (ADC) with programmable transfer functions is presented. Building upon prior art, a two‐step successive approximation technique is used to implement a piecewise‐linear ...
S. Sengupta, M.L. Johnston
doaj +1 more source
A Novel Biphasic-Current-Pulse Calibration Technique for Electrical Neural Stimulation [PDF]
, 2014 One of the major challenge in neural prosthetic device design is to ensure charge-balanced stimulation. This paper presents a new calibration technique to minimize the mismatch between anodic and cathodic current amplitudes.
Ren, MH, Wang, L, Wang, ZY, Zhang, J
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IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2022 This article explores a compute-in-memory (CIM) paradigm’s new application for cryogenic neural network. Using the 28-nm cryogenic transistor model calibrated at 4 K, the time-based CIM macro comprised of the following: 1) area-efficient unit ...
Dong Suk Kang, Shimeng Yu
doaj +1 more source
Energy‐efficient switching method for SAR ADCs with bottom plate sampling
Electronics Letters, 2016 A high energy‐efficiency capacitor switching scheme for successive approximation register (SAR) analogue‐to‐digital converters (ADCs) is presented. The switching method, verified on a 10‐bit SAR scheme that uses bottom plate sampling, achieves an average
Yulin Zhang +2 more
doaj +1 more source
Noise shaping Asynchronous SAR ADC based time to digital converter [PDF]
, 2018 Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits.
Katragadda, Sowmya
core +1 more source
IET Circuits, Devices and Systems, 2022 Mismatch in the binary‐weighted capacitive digital‐to‐analog converter (DAC) greatly affects the linearity of the successive‐approximation‐register (SAR) ADC by deteriorating the total harmonic distortion (THD).
Li Dong +8 more
doaj +1 more source
PixFEL: development of an X-ray diffraction imager for future FEL applications [PDF]
, 2017 A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm.
Battignani, Giovanni +21 more
core +1 more source
A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s [PDF]
, 2010 This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and
Elzakker, Michiel van +5 more
core +2 more sources
Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update [PDF]
, 2016 This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and ...
Pickering, J.
core +3 more sources