An asynchronous ternary logic signaling system [PDF]
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2003 This paper presents a new approach to an on-chip asynchronous transmission system suitable for next generation asynchronous on-chip networks. It implements multivalued logic to reduce the number of wires and a low-voltage swing for lower dynamic power dissipation.
T. Felicijan, Stephen B. Furber
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Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm [PDF]
, 2019 Logic synthesis has been increasingly important to accelerate the development of high-level systems. However, in multi-valued logic, logic synthesis methods that can process emerging devices are deficient.
Seokhyeong Kang +5 more
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Designing a Novel high-speed ternary-logic multiplier using GNRFET Technology [PDF]
Journal of Optoelectronical Nanostructures, 2023 :This paper presents a novel design of a ternary multiplierbased on graphene nanoribbon field-effect transistor(GNRFET). GNRFET, as a new material with superiorphysical and electronic properties, can be a good choiceinstead of conventional devices such ...
Zahra Rohani +1 more
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Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic [PDF]
, 2019 We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver ...
Seokhyeong Kang +8 more
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Spectral Response of Ternary Logic Netlists [PDF]
2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 2013 Past methods for computation of the spectrum of a multiple-valued logic network usually rely on first characterizing the network in terms of a switching function, secondly in mapping the function values to complex numbers, and thirdly in performing the computation resulting in the spectrum.
Mitchell A. Thornton +1 more
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A Novel Ternary Multiplier based on Ternary CMOS Compact Model [PDF]
, 2017 Multiple-valued logic (MVL) has potential advantages for energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuit designs.
Kang, Yesung +15 more
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Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders [PDF]
E3S Web of Conferences, 2023 This work presents comparison of ternary combinational digital circuits that reduce energy consumption in low-power VLSI (Very Large Scale Integration) design.
C. Venkataiah +6 more
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An Explanation for the Ternary Relation R in the Relational Semantics of Relevance Logic [PDF]
, 2015 Relational semantics is one of the most popular forms of semantics for relevance logic. However, this semantics, especially the ternary relation R lacks intuition, and that is why there are various interpretations for R.
Zhou, Beihai +3 more
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Verification and Testing Methods for Ternary Logic Circuits [PDF]
, 2022 MasterIn recent decades, complementary metal-oxide-semiconductor (CMOS) based binary digital systems have steadily improved in performance. However, the CMOS technology faces fundamental limitations as the feature size decreases.
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Ternary Logics Based on 2D Ferroelectric-Incorporated 2D Semiconductor Field Effect Transistors
Frontiers in Materials, 2022 Ternary logic has been proven to carry an information ratio 1.58 times that of binary logic and is capable to reduce circuit interconnections and complexity of operations.
Guangchao Zhao +9 more
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