Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs [PDF]
IEEE AccessThe application of artificial intelligence (AI) requires advanced computation to address complex problems. However, the improvement of binary computing systems supporting these applications is approaching their limits due to atomic-level scaling ...
Hyundong Lee +5 more
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Novel Ternary Logic Gates Design in Nanoelectronics [PDF]
Advances in Electrical and Electronic Engineering, 2019 In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is ...
Sajjad Etezadi, Seied Ali Hosseini
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Ternary combinational logic gate design based on tri-valued memristors
Frontiers in Physics, 2023 Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring.
Xiao-Jing Li +6 more
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Ternary logic in parallel multipliers [PDF]
The Computer Journal, 1972 The logic cost and speed of parallel multipliers implemented in both binary and ternary logic is studied. Binary operand lengths of 8 through 32 bits and the corresponding ternary digit range of 6 through 21 are considered. For the particular design technique used, the b i i r y versions are slightly faster where the speed criterion is in terms of the ...
Zvonko G. Vranesic, V. Carl Hamacher
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DESIGN AND SYNTHESIS OF TERNARY LOGIC ELEMENTS
Компютерні системи та інформаційні технології, 2022 The aim of this paper is creating some ternary elements. The threshold element of ternary logic on bipolar transistors and elements of ternary systems based on it are considered. The main disadvantages of this approach are identified. The multi-threshold
LARYSA MARTYNOVYCH +3 more
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Novel High-Speed Ternary Logic Using Step-Shaped Threshold Switch [PDF]
, 2023 We presented the ternary logic using a threshold switch (TS) that enabled faster operation than the existing ternary concept and quantitatively compared it to binary logic in a 5-nm node.
백록현 +3 more
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Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction [PDF]
, 2020 Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect ...
Seokhyeong Kang +13 more
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Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits [PDF]
E3S Web of Conferences, 2023 Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits.
C. Venkataiah +6 more
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Design of ternary full-adder and full-subtractor using pseudo NCNTFETs
e-Prime: Advances in Electrical Engineering, Electronics and Energy, 2023 Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular.
SV RatanKumar +2 more
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Two Efficient Ternary Adder Designs Based On CNFET Technology [PDF]
Computer and Knowledge Engineering, 2021 Full adder is one of the essential circuits among the various processing elements used in VLSI and other technologies circuits, because they are mainly employed in other arithmetic circuits, such as multi-digit adders, subtractors, and multipliers.
Masoud Mahjoubi +3 more
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