Designing a Novel high-speed ternary-logic multiplier using GNRFET Technology [PDF]
:This paper presents a novel design of a ternary multiplierbased on graphene nanoribbon field-effect transistor(GNRFET). GNRFET, as a new material with superiorphysical and electronic properties, can be a good choiceinstead of conventional devices such ...
Zahra Rohani +1 more
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Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders [PDF]
This work presents comparison of ternary combinational digital circuits that reduce energy consumption in low-power VLSI (Very Large Scale Integration) design.
C. Venkataiah +6 more
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Spectral Response of Ternary Logic Netlists [PDF]
Past methods for computation of the spectrum of a multiple-valued logic network usually rely on first characterizing the network in terms of a switching function, secondly in mapping the function values to complex numbers, and thirdly in performing the computation resulting in the spectrum.
Mitchell A. Thornton +1 more
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Developed ternary processor units based on analog models of ternary logic elements [PDF]
Background and Objectives: The transition of digital technology from a binary base to a ternary number system, that is, the use of three possible states within one digit – false/uncertain/true – allows one to obtain a number of advantages and,
Semenov, Andrey Andreevich +2 more
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New ternary inverter with memory function using silicon feedback field-effect transistors
In this study, we present a fully complementary metal–oxide–semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a positive feedback loop by carrier accumulation in
Jaemin Son, Kyoungah Cho, Sangsig Kim
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Ternary Logics Based on 2D Ferroelectric-Incorporated 2D Semiconductor Field Effect Transistors
Ternary logic has been proven to carry an information ratio 1.58 times that of binary logic and is capable to reduce circuit interconnections and complexity of operations.
Guangchao Zhao +9 more
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An RTL-Based General Synthesis Methodology for Device-Independent Ternary Logic Circuits
Ternary logic circuits are considered a high-potential alternative that can continue the technological advance of binary logic. Current studies in ternary logic focus on two aspects: One focuses on designing specific ternary circuits (such as adders ...
Hanmok Park +3 more
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Implementation and Applications of a Ternary Threshold Logic Gate
Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a designer. Most of the times, the designer sacrifices power consumption and chip area to improve delay for a given technology node. To overcome this problem, we propose a ternary threshold logic gate.
Ahmet Unutulmaz, Cem Ünsalan
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Ternary instantaneous noise-based logic
One of the possible representations of three-valued instantaneous noise-based logic is proposed. The third value is an uncertain bit value, which can be useful in artificial intelligence applications. There is a forth value, too, that can represent a non-existing bit (vacuum-state) that is the same (1 numeric value) for all bits, however that is a ...
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From static ternary adders to high-performance race-free dynamic ones
This study explores the suitability of dynamic logic style in ternary logic. It presents high-performance dynamic ternary half and full adders, which are essential components in computer arithmetic.
Shirin Rezaie +4 more
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