Results 41 to 50 of about 29,463 (289)
Design and Simulation of Balanced Ternary Priority Encoder
Memories - Materials, Devices, Circuits and SystemsThe priority encoder is a frequently used circuit in binary logic and is mostly used for interrupt handling and other priority resolving tasks. On the other hand, Ternary computing has tremendous potential for handling a wide variety of functions ...
Aadarsh Ganesh Goenka +3 more
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Analog models for ternary combinational logic elements [PDF]
Известия Саратовского университета. Новая серия: ФизикаBackground and Objectives: It is already obvious today that the performance of modern microprocessors is approaching its limit. Increasing the clock frequency and increasing the performance of the transistors included in them by reducing their size is ...
Semenov, Andrey Andreevich +2 more
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Comments on “High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits”
IEEE Access, 2020 In the above article [1], R. A. Jaber et al. present the designs of ternary logic circuits based on CNTFET technology. The motivation for designing ternary gates is based on the following assumption quoted in the abstract: “Moreover, multi-valued ...
Daniel Etiemble
doaj +1 more source
Minimal Negation in the Ternary Relational Semantics [PDF]
, 2005 Minimal Negation is defined within the basic positive relevance logic in the relational ternary semantics: B+. Thus, by defining a number of subminimal negations in the B+ context, principles of weak negation are shown to be isolable.
Méndez, José M. +2 more
core +1 more source
Intein‐based modular chimeric antigen receptor platform for specific CD19/CD20 co‐targeting
Molecular Oncology, EarlyView.CARtein is a modular CAR platform that uses split inteins to splice antigen‐recognition modules onto a universal signaling backbone, enabling precise, scarless assembly without re‐engineering signaling domains. Deployed here against CD19 and CD20 in B‐cell malignancies, the design supports flexible multi‐antigen targeting to boost T‐cell activation and
Pablo Gonzalez‐Garcia +9 more
wiley +1 more source
A Reliable and Energy-Efficient Nonvolatile Ternary Memory Based on Hybrid FinFET/RRAM Technology
IEEE Access, 2022 With the successful development of information technology, particularly in big data and neural network scopes, the appetency for denser memory compositions has exponentially outreached.
Aram Yousefi +2 more
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CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE [PDF]
, 2015 This project report focuses on the multiple-value logic (MVL) or commonly known as ternary logic gates by using carbon nanotube (CNT) FETs devices (CNTFETs).
Ee, Poey Guan
core
A Q‐Learning Algorithm to Solve the Two‐Player Zero‐Sum Game Problem for Nonlinear Systems
International Journal of Adaptive Control and Signal Processing, Volume 39, Issue 3, Page 566-581, March 2025.A Q‐learning algorithm to solve the two‐player zero‐sum game problem for nonlinear systems. ABSTRACT This paper deals with the two‐player zero‐sum game problem, which is a bounded L2$$ {L}_2 $$‐gain robust control problem. Finding an analytical solution to the complex Hamilton‐Jacobi‐Issacs (HJI) equation is a challenging task.
Afreen Islam +2 more
wiley +1 more source
Cybergeo, 2018 Our previous papers showed the interest of using both structural binary logic and, particularly, processual ternary logic to apprehend resilience in urban geography. This paper is an in depth exploration of the association of S.
Henri Reymond, Colette Cauvin
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Synthesis of Reversible Circuits from a Subset of Muthukrishnan-Stroud Quantum Realizable Multi-Valued Gates [PDF]
, 2004 We present a new type of quantum realizable reversible cascade. Next we present a new algorithm to synthesize arbitrary single-output ternary functions using these reversible cascades.
Denler, Nicholas +3 more
core +1 more source