Results 211 to 220 of about 84,742 (270)

A Thermodynamically Favoured Molecular Computer: Robust, Fast, Renewable, Scalable

Stérin T, Eshra A, Adio J, Evans CG, Woods D.   +4 more
europepmc   +1 more source

Some of the next articles are maybe not open access.

Related searches:

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits

IEEE Transactions on Circuits and Systems I: Regular Papers, 2020
We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value ...
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang   +4 more
openaire   +3 more sources

Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms

IEEE Transactions on Emerging Topics in Computing
Multi-valued logic (MVL) circuits, especially the ternary logic circuits, have attracted great attention in recent years due to their higher information density than binary logic systems. However, the basic construction method for MVL circuit standard cells and the CMOS fabrication possibility/compatibility issues are still to be addressed.
Zhao, Guangchao, Zeng, Zhiwei, Wang, Xingli, Qoutb, Abdelrahman, Coquet, Philippe, Friedman, Eby, Tay, Beng Kang, Huang, Mingqiang   +7 more
openaire   +2 more sources

Design Methodologies for Ternary Logic Circuits

2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 2018
Ternary logic has advantage over binary circuits with respect to area and interconnect complexity. CNFET technology is ideal to implement ternary logic circuits because the threshold voltage of CNFETs depends on the physical dimensions of their channel. This work presents new approach to design CNFET-based ternary logic circuits. This approach uses 2:1
Chetan Kumar Vudadha, MB Srinivas
openaire   +2 more sources

Design of ternary logic circuits using CNTFET

2018 International Symposium on Devices, Circuits and Systems (ISDCS), 2018
The work in this paper presents the design of ternary logic circuits using MOSFET-like carbon nanotube field effect transistor (CNTFET). The ternary logic is one of multivalued logic circuits which is the best substitute for traditional binary logic because of its low power consumption and low power delay product (PDP) resulting from reduced complexity
Debaprasad Das, Anirban Banerjee, Vikash Prasad   +2 more
openaire   +2 more sources

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate.
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang   +3 more
openaire   +2 more sources

A Ternary Decision Diagram (TDD)-Based Synthesis Approach for Ternary Logic Circuits

Journal of The Institution of Engineers (India): Series B, 2019
Ternary reversible logic synthesis has started gaining the attention of researchers in recent years because of its distinct advantages over binary reversible logic synthesis. However, the existing methods for the synthesis of ternary reversible logic circuits are applicable only to smaller benchmarks.
P. Mercy Nesa Rani, Abhoy Kole, Kamalika Datta   +2 more
openaire   +2 more sources

Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits

IEEE Transactions on Nanotechnology, 2018
In existing CNFET-based design methodologies that are used to implement ternary logic circuits, ternary signals are first converted to binary signals, which are then passed through binary gates and an encoder to get the final ternary output. In a ternary circuit, encoder is used to convert intermediate binary signals to final ternary outputs.
Chetan Vudadha, Srinivasan Rajagopalan, Aditya Dusi, P. Sai Phaneendra, M. B. Srinivas   +4 more
openaire   +2 more sources

Novel Approach to Design DPL-based Ternary Logic Circuits

2018 IEEE Electron Devices Kolkata Conference (EDKCON), 2018
Present paper introduces a novel strategy to design Double Pass-transistor Logic (DPL)based Ternary (base-3)logic circuit in favour of wave-pipelined applications. Ternary can be a feasible candidate to replace conventional binary (base-2)number system due to faster computation, reduced interconnect complexity, reduced fan-in/fan-out, less storage ...
Narendra Deo Singh, Rakesh Kumar Singh, Rahul Raj, Shivam Jyoti, Aloke Saha   +4 more
openaire   +2 more sources

Design of Ternary Logic Circuits Using GNRFET and RRAM

Circuits, Systems, and Signal Processing, 2023
Shaik Javid Basha, P. Venkatramana
openaire   +2 more sources