Results 121 to 130 of about 1,665 (175)

Comparison of power and performance for the TFET and MOSFET and considerations for P-TFET

2011 11th IEEE International Conference on Nanotechnology, 2011
A detailed circuit assessment of Tunneling Field Effect Transistors (TFET) versus MOSFET transistors operating at a supply voltage near device threshold is reported, including the consideration of P-TFET device design. 20nm gate-length InAs TFET and Si MOSFET device characteristics are simulated and used in circuit simulations.
Uygar E. Avci, Rafael Rios, Kelin J. Kuhn, Ian A. Young   +3 more
openaire   +1 more source

Challenges and Solutions of the TFET Circuit Design

IEEE Transactions on Circuits and Systems I: Regular Papers, 2020
Steep sub-threshold interband tunnel field-effect transistors (TFETs) are promising candidates for low-supply voltage applications with better performance than the traditional complementary metal oxide semiconductor (CMOS). However, some of the shortcomings of TFETs also severely limit their application.
Zhiting Lin, Panpan Chen, Le Ye, Xu Yan, Lanzhi Dong, Shuguang Zhang, Zhou Yang 0009, Chunyu Peng, Xiulong Wu, Junning Chen   +9 more
openaire   +1 more source

Comparative Analysis of Double Gate TFET and Hetero Dielectric Double Gate TFET

2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC), 2018
This paper compares and analyzes the performance of Hetero Dielectric Double Gate TFET (HD-DG TFET) with that of conventional DG-TFET using TCAD simulation. This paper reports the influence of various hetero dielectric materials and source doping concentrations on drain current. A low leakage current (IOFF) is observed with an improved on current and a
Sushree Anusmita Sahu, S. K. Mohapatra, Rupam Goswami   +2 more
openaire   +1 more source

Drain-conductance optimization in nanowire TFETs

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012
In this work we examine the problem of the nonlinear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic operation and severely degrades the device dynamic properties compared with standard CMOS FETs. The problem is investigated with the help of an analytical model which
GNANI, ELENA, REGGIANI, SUSANNA, GNUDI, ANTONIO, BACCARANI, GIORGIO   +3 more
openaire   +1 more source

Intrinsic voltage gain of Line-TFETs and comparison with other TFET and MOSFET architectures

2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016
In this work the intrinsic voltage gain (AV) is for the first time experimentally analyzed for a planar Line-TFETs and its performance is compared with different MOSFET and point TFET architectures (FinFET and GAA:Gate-All-Around) at both room and high temperatures.
P. G. D. Agopian, J. A. Martino, R. Rooyackers, A. Vandooren, E. Simoen, A. Thean, C. Claeys   +6 more
openaire   +1 more source

Compact Models of TFETs

2016
Rapid developments in the TFETs’ process and rising interests in evaluating their potential in low-power circuits/systems require a TFET compact model for SPICE simulations. In this chapter, we discuss the essential device physics of TFETs, propose necessary simplifications of their complex operations, and develop a core model for homojunction TFETs ...
Zhang, Lining, Chan, Man Sun
openaire   +2 more sources

16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016
This paper presents for the first time a TFET/CMOS hybrid CAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications like the IoT (Internet of Things). Proposed design is low power, area efficient and re-configurable i.e. can either be used as CAM or normal SRAM or as a combination of both.
Gupta, Navneet, Makosiej, Adam, Vladimirescu, Andrei, Amara, Amara, Anghel, Costin   +4 more
openaire   +2 more sources

TFETs for Analog Applications

2018
Data has been reported on the analog performance of full silicon devices, silicon-based nanowire TFETs with different source compositions and line-Tunnel field-effect transistor (FET) (TFET). Although the tunnel-FET devices were developed for digital applications, some researchers have demonstrated their potential for analog circuit design. However, it
Marcio Dalla Valle Martino, Paula Ghedini Der Agopian, Joao Antonio Martino, Eddy Simoen, Cor Claeys   +4 more
openaire   +1 more source

Magnetic TFET (MAG-TFET)

2022 International Electrical Engineering Congress (iEECON), 2022
Thanet Boonlua, Amporn Poyai, Toempong Phetchakul   +2 more
openaire   +1 more source

An Optimized Hetrojunction Dopingless TFET

2018 International Conference on Emerging Trends and Innovations In Engineering And Technological Research (ICETIETR), 2018
The concept of dopingless TFET (DL TFET) is an potential solution methodology against problems due to RDFs. However., the low ON-state current ( $I_{ON}$ ) is still a problem in physically doped TFET and it becomes severe for DL TFET due to the existence of barrier at the gap between source and gate electrodes.
A Meera, Nisha Kuruvilla, T E Ayoob Khan
openaire   +1 more source