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2020
Integrated circuits, especially analog circuits, are highly sensitive to process, voltage, and temperature (PVT) variations. The information processed by analog circuits is often embedded in the amplitude of the waveforms, which requires circuits with high precision and high linearity. On the other hand, analog signal processing in time domain, such as
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Integrated circuits, especially analog circuits, are highly sensitive to process, voltage, and temperature (PVT) variations. The information processed by analog circuits is often embedded in the amplitude of the waveforms, which requires circuits with high precision and high linearity. On the other hand, analog signal processing in time domain, such as
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Designing Time-to-Digital Converter for Asynchronous ADCs
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, 2007Time-to-digital converter designing and analysis for asynchronous ADCs is discussed in the paper. The proposed ADC utilizes two-level conversion scheme consisting in duty-cycle modulation and subsequent time-to-digital conversion (TDC). Three concepts of the asynchronous ADC digital serial output interface are presented.
Dariusz Koscielnik, Marek Miskowicz
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Background on Time-to-Digital Converters
2015For the first time, a third-order noise shaping concept has been successfully implemented in the design of time-to-digital converters (TDCs). Two 1-1-1 multistage noise shaping (MASH) \(\Delta\Sigma\) TDCs are presented in this chapter. Third-order time domain noise shaping has been adopted by the TDCs to achieve better than 6 ps resolution.
Ying Cao, Paul Leroux, Michiel Steyaert
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An optical method for the time-to-digital converters characterization
2015 17th International Conference on Transparent Optical Networks (ICTON), 2015Measurement of the distribution random error describing a high precision multi-tapped delay lines with coding registers module is important from the perspective of construction high-resolution time-to-digital converters. Knowledge of this distribution allows to optimize the process of implementation Multi-Tapped Delay Lines in programmable structures ...
Robert Frankowski +2 more
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Synchronization in a Multilevel CMOS Time-to-Digital Converter
IEEE Transactions on Circuits and Systems I: Regular Papers, 2009Accurate time-to-digital conversion is typically based on determining the positions of the timing signals within the period of an accurate clock with digital delay-line interpolators. In order to save circuit area and to improve single-shot precision to the picosecond level, multilevel interpolators can be used.
Jussi-Pekka Jansson +2 more
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Interpolating time-to-digital converters
Optoelectronics, Instrumentation and Data Processing, 2008Principles of conversion of single time intervals into a digital code with the use of interpolation of the reference period for reducing the sampling error are reviewed. Interpolating converters are based on integrated digital delay lines and phase interpolation elements, which allow the resolution lower than the propagation delay of a single logical ...
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Measuring metastability using a time-to-digital converter
2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2017In view of the numerous clock domain crossings found in modern systems-on-chip and multicore architectures precise metastability characterization is a fundamental task. We propose a conceptually novel approach for the experimental assessment of upset rate over resolution time that is usually employed to extract the relevant characteristics.
Thomas Polzer +2 more
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2013
Dynamic development in science and technology in the second half of the twentieth century caused, among others, an increase in the interest in methods and techniques for precise measurement of time interval that elapses between two physical events.
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Dynamic development in science and technology in the second half of the twentieth century caused, among others, an increase in the interest in methods and techniques for precise measurement of time interval that elapses between two physical events.
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High-precision Time-to-Digital Converters in a FPGA device
2008 IEEE Nuclear Science Symposium Conference Record, 2008The construction and design process of a highresolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision on the measurement by interpolating time within the system clock cycle.
A. Aloisio +5 more
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Design of Time-to-Digital Converter Output Interface
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008A design of time-to-digital converter output interface for ADCs with asynchronous sigma-delta modulation is presented in details in the paper. The concept of the digital interface with double data buffering and asynchronous serial link is carefully explained on the basis of the schematics of particular functional blocks.
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