Results 151 to 160 of about 3,473 (197)

A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation

International Test Conference in Asia, 2023
This paper presents a physically unclonable function (PUF) using flash time-to-digital converter (TDC) with linearity self-calibration. The proposed PUF utilizes that the variation of delay of delay elements of TDC is unique to the device and unclonable.
Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, A. Kuwana, Takayuki Nakatani, K. Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa   +12 more
semanticscholar   +1 more source

Design and Experiment of Ultrasonic Anemometer Using TDC-GP2 Time-to-Digital Converter

Key Engineering Materials, 2014
An ultrasonic anemometer using TDC-GP2 high-accuracy time measuring chip is studied in this paper, the design of software and hardware parts and principle of flying time measurement using TDC-GP2 chip are also discussed in detail. Under this scheme, a prototype has been fabricated, with simpler circuit architecture.
Han Yu Du, Ming Qin
openaire   +1 more source

A Low-Cost FPGA-Based Coarse-Fine Counting Time-to-Digital Converter With External High-Precision Reference Clock

IEEE Transactions on Instrumentation and Measurement, 2023
A new coarse-fine counter time-to-digital converter (TDC) architecture and its implementation techniques for high-precision time-interval measurement are presented. Multicoarse counters and one fine counter are combined in our TDC architecture.
Xin Yu, Songtao Chang, W. Li, Haojie Xia
semanticscholar   +1 more source

A 4.8 ps root-mean-square resolution time-to-digital converter implemented in a 20 nm Cyclone-10 GX field-programmable gate array.

Review of Scientific Instruments, 2022
It is difficult to improve the resolution and precision of a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) in time interval measurement.
Xin Yu, Haojie Xia, W. Li, Jin Zhang, Songtao Chang   +4 more
semanticscholar   +1 more source

A Novel 12-Bit 0.6-mW Two-Step Coarse-Fine Time-to-Digital Converter

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2022
A novel two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation analog-to-digital converter (SAR-ADC) for the fine stage ...
Zhaoyuan Wang, Yeran Jin, Bo Zhou
semanticscholar   +1 more source

A compact Time-to-Digital Converter (TDC) module with 10 ps resolution and less than 1.5% LSB DNL

IEEE Photonics Conference 2012, 2012
We present a low-power Time-to-Digital Converter (TDC) module that provides 10 ps timing resolution, DNL better than 1.5% LSB and 160 ns dynamic range within a compact 6 cm × 6 cm × 8 cm housing. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via ...
MARKOVIC, BOJAN, VILLA, FEDERICA ALBERTA, BELLISAI, SIMONE, BRONZI, DANILO, SCARCELLA, CARMELO, BOSO, GIANLUCA, BAHGAT SHEHATA, ANDREA, DELLA FRERA, ADRIANO, TOSI, ALBERTO   +8 more
openaire   +1 more source

7.2 A 48 ×4013.5 mm Depth Resolution Flash LiDAR Sensor with In-Pixel Zoom Histogramming Time-to-Digital Converter

IEEE International Solid-State Circuits Conference, 2021
3D imaging technologies have become prevalent for diverse applications such as user identification, interactive user interfaces with AR/VR devices, and self-driving cars.
Bumjun Kim, Seonghyeok Park, J. Chun, Jaehyuk Choi, Seong-Jin Kim   +4 more
semanticscholar   +1 more source

Design and Calibration Techniques for a Multichannel FPGA-Based Time-to-Digital Converter in an Object Positioning System

IEEE Transactions on Instrumentation and Measurement, 2021
A multichannel field-programmable gate array (FPGA)-based time-to-digital converter (TDC) and its calibration techniques are presented. Herein, a frequency-tracker-based sliding-scale technique and a moving-average filter to improve the linearity and ...
Kyu-Jin Choi, Dong-Woo Jee
semanticscholar   +1 more source

A resource-saving dual channel time-to-digital converter with shared tapped delay line in FPGAs

Journal of Instrumentation, 2021
A resource-saving dual channel time-to-digital converter (TDC) in field programmable gate array (FPGA) is presented in this paper. The presented TDC is formed by cascading a channel waveform generator (CWG) and a tapped delay line.
Y. Jiao, Q. Zhang, W. Chen, L. Zhou, C. Chen   +4 more
semanticscholar   +1 more source

A High-Resolution Time-Based Resistance-to-Digital Converter with TDC and Counter

Midwest Symposium on Circuits and Systems, 2018
This paper presents a high resolution time-based resistance-to-digital converter for amp-less high-precision sensor application. In order to solve the trade-off between resolution and bandwidth, a time-to-digital converter (TDC) is combined with a ...
S. Nakagawa, Kaito Horikoshi, H. Ishikuro   +2 more
semanticscholar   +1 more source