Results 171 to 180 of about 1,742 (210)
High-rate quantum key distribution with compact state preparation and detection. [PDF]
Fan-Yuan GJ +12 more
europepmc +1 more source
A 4-Channel 0.23<i>mm</i> <sup>2</sup> Voltage-to-Time Converter AFE with 3.7<i>μVrms</i> Noise and 480<i>nW</i> Galvanic Impulse Uplink. [PDF]
Bandali M, Riley M, Johnson BC.
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Quantum entanglement network enabled by a state-multiplexing quantum light source. [PDF]
Fan YR +11 more
europepmc +1 more source
Integrated Ultrasound Device for Precision Bladder Volume Monitoring via Acoustic Focusing and Machine Learning. [PDF]
Cao LL, Wang FW, Xue J, Liu F, Jin ML.
europepmc +1 more source
Design and implementation of a high resolution, multi-hit time-to-digital converter (TDC) on FPGA
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2011 IEEE International Instrumentation and Measurement Technology Conference, 2011
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
exaly +5 more sources
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
exaly +5 more sources
NORCHIP 2010, 2010
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Salim Al-Ahdab +2 more
openaire +3 more sources
This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Salim Al-Ahdab +2 more
openaire +3 more sources
IEEE Transactions on Nuclear Science, 2014
This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain.
Weibin Pan, Guanghua Gong, Jianmin Li
openaire +3 more sources
This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain.
Weibin Pan, Guanghua Gong, Jianmin Li
openaire +3 more sources
2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2012
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
openaire +3 more sources
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Mäntyniemi Antti +2 more
openaire +3 more sources
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2012
Abstract The paper presents and compares FPGA implementations of Time-to-Digital Converters (TDC) developed in the framework of the XNAP project, an international collaboration building Avalanche Photo Diode based area X-ray detectors. We are revisiting and presenting updated results achieved with recent components of two different TDC architectures ...
C. Hervé, J. Cerrai, T. Le Caër
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Abstract The paper presents and compares FPGA implementations of Time-to-Digital Converters (TDC) developed in the framework of the XNAP project, an international collaboration building Avalanche Photo Diode based area X-ray detectors. We are revisiting and presenting updated results achieved with recent components of two different TDC architectures ...
C. Hervé, J. Cerrai, T. Le Caër
openaire +3 more sources

