Results 171 to 180 of about 117,069,527 (207)
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2011 IEEE International Instrumentation and Measurement Technology Conference, 2011
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Juha Kostamovaara, Antti Mäntyniemi
exaly +3 more sources
This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Juha Kostamovaara, Antti Mäntyniemi
exaly +3 more sources
2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
exaly +3 more sources
Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly ...
Tingbing Ouyang +4 more
exaly +3 more sources
A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module
Journal of Instrumentation, 2012The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine ...
Büchele, Maximilian +6 more
openaire +2 more sources
A compact Time-to-Digital Converter (TDC) module with 10 ps resolution and less than 1.5% LSB DNL
IEEE Photonics Conference 2012, 2012We present a low-power Time-to-Digital Converter (TDC) module that provides 10 ps timing resolution, DNL better than 1.5% LSB and 160 ns dynamic range within a compact 6 cm × 6 cm × 8 cm housing. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via ...
MARKOVIC, BOJAN +8 more
openaire +1 more source
A 20-ps temperature compensated Time-to-Digital Converter (TDC) implemented in FPGA
2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC), 2013This paper presents a temperature compensation design for carry chain based Time-to-Digital Converter (TDC) in FPGA. The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain which shows all TDC channels have the ...
openaire +1 more source
INTERNATIONAL CONFERENCE ON SMART STRUCTURES AND SYSTEMS - ICSSS'13, 2013
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement.
Mahantesh P. Mattada, Hansraj Guhilot
openaire +1 more source
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement.
Mahantesh P. Mattada, Hansraj Guhilot
openaire +1 more source
2009 4th IEEE Conference on Industrial Electronics and Applications, 2009
This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay ...
Tingcun Wei, Christine Hu-Guo, Yann Hu
exaly +2 more sources
This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay ...
Tingcun Wei, Christine Hu-Guo, Yann Hu
exaly +2 more sources
IEEE Journal of Solid-State Circuits, 2019
A phenomenon called parallel-output misalignment (POM), which intrinsically occurs in ring-type time-to-digital converters (TDCs) like gated-ring oscillator (GRO) or Vernier-ring TDCs, is discussed in this paper. We found that the phase noise caused by POM error may be larger than that due to quantization error by up to 22 dB or even more.
Tuoxin Wang +2 more
openaire +1 more source
A phenomenon called parallel-output misalignment (POM), which intrinsically occurs in ring-type time-to-digital converters (TDCs) like gated-ring oscillator (GRO) or Vernier-ring TDCs, is discussed in this paper. We found that the phase noise caused by POM error may be larger than that due to quantization error by up to 22 dB or even more.
Tuoxin Wang +2 more
openaire +1 more source
2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2012
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Juha Kostamovaara +2 more
exaly +2 more sources
This paper describes a digital-to-time converter (DTC) architecture that can be used as interpolator in a time-to-digital converter (TDC). The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range.
Juha Kostamovaara +2 more
exaly +2 more sources
2013
In this paper, the Cramér-Rao Lower Bound (CRLB) on the variance of time interval duration estimators is derived for synchronous Time-to-Digital (TDC) converters, based on a coarse counter, keeping into account the effect of noise affecting the TDC clock period. The model has been validated using Montecarlo analysis.
G. De Angelis +2 more
openaire +1 more source
In this paper, the Cramér-Rao Lower Bound (CRLB) on the variance of time interval duration estimators is derived for synchronous Time-to-Digital (TDC) converters, based on a coarse counter, keeping into account the effect of noise affecting the TDC clock period. The model has been validated using Montecarlo analysis.
G. De Angelis +2 more
openaire +1 more source