Results 191 to 200 of about 1,742 (210)

A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module

Journal of Instrumentation, 2012
The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine ...
Büchele, Maximilian, Fischer, Horst, Gorzellik, Matthias, Herrmann, Florian, Königsmann, Kay, Schill, Christian, Schopferer, Sebastian   +6 more
openaire   +2 more sources

Design and Implementation of a Digital Phase-Locked Loop (DPLL) with Vernier Time-to-Digital Converter (TDC) for Dynamic Frequency Selection

2024 Global Conference on Communications and Information Technologies (GCCIT)
Akshay Kumar M V, Rajath Vasudevamurthy
openaire   +3 more sources

A compact Time-to-Digital Converter (TDC) module with 10 ps resolution and less than 1.5% LSB DNL

IEEE Photonics Conference 2012, 2012
We present a low-power Time-to-Digital Converter (TDC) module that provides 10 ps timing resolution, DNL better than 1.5% LSB and 160 ns dynamic range within a compact 6 cm × 6 cm × 8 cm housing. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via ...
MARKOVIC, BOJAN, VILLA, FEDERICA ALBERTA, BELLISAI, SIMONE, BRONZI, DANILO, SCARCELLA, CARMELO, BOSO, GIANLUCA, BAHGAT SHEHATA, ANDREA, DELLA FRERA, ADRIANO, TOSI, ALBERTO   +8 more
openaire   +1 more source

A 20-ps temperature compensated Time-to-Digital Converter (TDC) implemented in FPGA

2013 IEEE Nuclear Science Symposium and Medical Imaging Conference (2013 NSS/MIC), 2013
This paper presents a temperature compensation design for carry chain based Time-to-Digital Converter (TDC) in FPGA. The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain which shows all TDC channels have the ...
openaire   +1 more source

A high-resolution multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications

2009 4th IEEE Conference on Industrial Electronics and Applications, 2009
This paper presents the design of a wide-range multi-channel time-to-digital converter (TDC) for high-energy physics and biomedical imaging applications. The TDC architecture is based on coarse-fine two-level conversion scheme. Double 10-bit gray counters are designed for coarse conversion while a multiphase sampling technology based on array of delay ...
null Gao Wu, null Gao Deyuan, null Wei Tingcun, Christine Hu-Guo, null Yann Hu   +4 more
openaire   +1 more source

Area efficient vernier Time to Digital Converter(TDC) with improved resolution using identical ring oscillators on FPGA

INTERNATIONAL CONFERENCE ON SMART STRUCTURES AND SYSTEMS - ICSSS'13, 2013
We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement.
Mahantesh P. Mattada, Hansraj Guhilot
openaire   +1 more source

Analysis and Correction of Noise Injection Due to Parallel-Output-Misalignment (POM) Effects in Ring-Type Time-to-Digital Converters (TDCs)

IEEE Journal of Solid-State Circuits, 2019
A phenomenon called parallel-output misalignment (POM), which intrinsically occurs in ring-type time-to-digital converters (TDCs) like gated-ring oscillator (GRO) or Vernier-ring TDCs, is discussed in this paper. We found that the phase noise caused by POM error may be larger than that due to quantization error by up to 22 dB or even more.
Tuoxin Wang, John W. M. Rogers, Krste Mitric   +2 more
openaire   +1 more source

Area efficient time to digital converter (TDC) architecture with double ring-oscillator technique on FPGA for fluorescence measurement application

2011 IEEE Recent Advances in Intelligent Computational Systems, 2011
We present an area efficient Time to Digital Converter (TDC) yielding a high resolution of nearly 10ps. The TDC architecture reported in this paper comprises of coarse measurement using system clock and two controllable oscillators for fine resolution measurement.
Mahantesh P Mattad, Hansraj Guhilot, Rajanish K Kamat   +2 more
openaire   +1 more source

On-Chip Real-Time Correction for a 20-ps Wave Union Time-To-Digital Converter (TDC) in a Field-Programmable Gate Array (FPGA)

IEEE Transactions on Nuclear Science, 2012
The latest delay chain-based FPGA TDCs can achieve resolutions around 10 ps. At such high levels of accuracy, delay chains become very sensitive to parasitic electromagnetic perturbations, including power supply voltage, temperature, and current surge. This paper describes how common-mode fast perturbation can deteriorate the spectra and make the root ...
Ji Qi, Hui Gong, Yinong Liu
openaire   +1 more source

Energy Efficient All-Digital Phase Locked Loop Architecture Design on High Resolution Fast Clocking Time to Digital Converter (TDC) Using Model Prescient Control (MPC) Technique

Wireless Personal Communications, 2018
Phase locked loops (PLLs) are utilized as a part of clock recovery and frequency synthesis. Entirely digital PLLs are more reasonable for the solid execution with different circuits contrasted with the customary usage of the PLLs. The all-digital PLLs are additionally autonomous of process varieties and can be efficiently ported to various innovations.
T. M. Sathish Kumar, P. S. Periasamy
openaire   +1 more source