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Silicon tunneling field-effect transistors with tunneling in line with the gate field

IEEE Electron Device Letters, 2013
We present experimental results on the fabrication and characterization of vertical Si tunneling field-effect transistors (TFETs) in a device geometry with tunneling in line with the gate field. Compared to vertical Si TFETs without this geometry modification, on-currents are increased by more than one order of magnitude with ION = 1.1 μA/μm at VDS = 0.
FISCHER, IA   +7 more
openaire   +2 more sources

Tunnel Field Effect Transistor with Ferroelectric Gate Insulator

Journal of Nanoscience and Nanotechnology, 2019
Ferroelectric tunnel field effect transistor (Fe-TFET) having improved DC performance in comparison to the conventional TFET (c-TFET) is proposed and investigated through the technology computer-aided design (TCAD) simulation. By inserting ferroelectric material into the gate insulator of TFET, enhanced on-current (Ion) is obtained. It is attributed to
Kitae, Lee   +7 more
openaire   +2 more sources

A simulation study of vertical tunnel field effect transistors

2011 9th IEEE International Conference on ASIC, 2011
We report a simulation study of the characteristics of a new tunnel field effect transistor (TFET), i.e., vertical TFET (VTFET). The new VTFET has a different working principle compared with the traditional lateral TFET (LTFET), which most of the recent studies are focused on.
Zhong-Fang Han, Guo-Ping Ru, Gang Ruan
openaire   +1 more source

III–V heterostructure tunnel field-effect transistor

Journal of Physics: Condensed Matter, 2018
Abstract The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs.
C Convertino   +4 more
openaire   +2 more sources

Vertical Tunnel Field-Effect Transistor with Polysilicon Layer

Journal of Nanoscience and Nanotechnology, 2019
In this paper, a novel structure of tunnel field-effect transistors (TFETs) is proposed. The proposed device has an intrinsic polysilicon layer located in the overlap region between the source and the gate, which can increase the tunneling area and overcome the low ON-current drawback of the conventional TFET.
Won Joo, Lee   +6 more
openaire   +2 more sources

Novel Tunnel Field Effect Transistors

This research aims to explore the complex challenges regarding reliability and scalability in Heterojunction Dual Gate Vertical Tunnel Field Effect Transistors (HJDGV-TFET). Specifically, it focuses on comparing the hetero buried and stacked buried configurations.
P. Suveetha Dhanaselvam   +3 more
openaire   +1 more source

Axial SiGe Heteronanowire Tunneling Field-Effect Transistors

Nano Letters, 2012
We present silicon-compatible trigated p-Ge/i-Si/n-Si axial heteronanowire tunneling field-effect transistors (TFETs), where on-state tunneling occurs in the Ge drain section, while off-state leakage is dominated by the Si junction in the source. Our TFETs have high I(ON) ~ 2 μA/μm, fully suppressed ambipolarity, and a subthreshold slope SS ~ 140 mV ...
Son T, Le   +6 more
openaire   +2 more sources

Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current

IEEE Electron Device Letters, 2009
We report the first study of the effect of strain on tunneling field-effect transistor (TFET) characteristics. Double-gate silicon TFETs were employed. It was found that tensile strain increases the drain current, whereas compressive strain reduces the drain current.
Guo, P.-F.   +6 more
openaire   +1 more source

Tunneling Field Effect Transistor Technology

2016
This book provides a single-source reference to the state-of-the art in tunneling field effect transistors (TFETs). Readers will learn the TFETs physics from advanced atomistic simulations, the TFETs fabrication process and the important roles that TFETs will play in enabling integrated circuit designs for power efficiency.
Zhang, Lining, Chan, Mansun
openaire   +2 more sources

Fabrication of epitaxial tunnel junction on tunnel field effect transistors

2019 19th International Workshop on Junction Technology (IWJT), 2019
With an increase in the amount of collected and modified data in today’s "big data" era, the demand for calculation resources in both "cloud" and "edge" has also increased. Circuits consume high power when calculating large amount of data. Presently, advanced microchips consume over 100 W of power, which is a critical problem of realizing the big data ...
Y. Morita   +3 more
openaire   +1 more source

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