Results 21 to 30 of about 30,856 (159)
Translating BIF into VHDL : algorithms and examples [PDF]
This report describes an algorithm for automatically translating BIF system-level behavioral descriptions to behavioral VHDL. BIF is a new intermediate representation for behavioral synthesis, based on annotated state tables that supports user control of
Cho, Joong Hwee+2 more
core
Innovative Hardware Accelerator Architecture for FPGA‐Based General‐Purpose RISC Microprocessors
Reconfigurable computing (RC) theory aims to take advantage of the flexibility of general‐purpose processors (GPPs) alongside the performance of application specific integrated circuits (ASICs). Numerous RC architectures have been proposed since the 1960s, but all are struggling to become mainstream.
Ehsan Ali, Iouliia Skliarova
wiley +1 more source
FPGA‐Based Realization of Intelligent Escalator Controller Using Artificial Neural Network
In this work, a proposed intelligent controller has been designed and implemented for a prototype of four stair‐step escalator. The required task of this controller is to manage the supplied power of driving motor of the escalator according to the applied load on the stair‐steps, which is represented by the number of persons standing on the stair‐steps.
Azzad Bader Saeed+3 more
wiley +1 more source
A literature review on V2X communications security: Foundation, solutions, status, and future
The article first introduces the development history of the past Internet of Vehicles(IoV), summarizes some common V2X security threats, describes the development and application of the SM commercial algorithm in recent years, and finally, statistics and introduces the part of the development process of the security protocols currently used in IoV ...
Zuobin Ying+3 more
wiley +1 more source
Empowering talkative power technology in wireless power transfer with machine learning
In this article, we propose a model for talkative power (TP) in an implemented wireless power transfer (WPT) circuit designed for constant power load (CPL) applications that concurrently transmit power and information through a shared channel. Our innovative model considers critical factors such as load variations and limited receiver knowledge ...
Seyed Ali Mousavi+2 more
wiley +1 more source
FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration [PDF]
In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA.
Civit Balcells, Antón+3 more
core +1 more source
ABSTRACT In this paper, simultaneous transmission on two orthogonal antenna polarizations in a polarization division multiplexing (PDM) fashion is studied for wideband satellite communication links using dual‐polarization satellite receivers for the purpose of doubling the data rate. In order to mitigate the cross‐polarization interference (XPI), a new
Svilen Dimitrov+2 more
wiley +1 more source
VSS : a VHDL synthesis system [PDF]
This report describes a register transfer synthesis system that allows a designer to interact with the design process. The designer can modify the compiled design by changing the input description, selecting optimization and mapping strategies, or ...
Gajski, Daniel D., Lis, Joseph S.
core
Investigation on the performance of crushed tires as cement replacement in concrete [PDF]
The automobile has become an indispensable means of transportation for many households throughout the world. Thus, the disposal of vehicle tires represents a major environmental issue.
Abas, Nor Haslinda+2 more
core
The transient switching mismatch between the switch pairs S1 & S4 and S2 & S3 leads to average voltage deviations during turn‐on and turn‐off instants, resulting in a net DC average voltage. This problem is compounded due to the low winding resistance of the transformer and eventually leads to saturation of the transformer. Abstract Dual active bridge (
Ganesan Perumal+2 more
wiley +1 more source