Results 1 to 10 of about 291 (113)

Modeling and Simulation for Predicting Thermo-Mechanical Behavior of Wafer-Level Cu-PI RDLs During Manufacturing [PDF]

open access: yesMicromachines
The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic ...
Xianglong Chu   +7 more
doaj   +2 more sources

Virtualization as a New Scaling Law for Semiconductor Devices Beyond Geometric Scaling. [PDF]

open access: yesSmall
AI‐enabled semiconductor scaling law. Virtualization emerges as an AI‐enabled scaling law for semiconductors, where progress depends on replacing physical iteration with credible virtual evidence. Surrogate modeling accelerates design‐space exploration, digital twins virtualize process learning, and defect‐to‐reliability inference advances ...
Wang Z   +8 more
europepmc   +2 more sources

Multi-Step Mechanical and Thermal Homogenization for the Warpage Estimation of Silicon Wafers [PDF]

open access: yesMicromachines
In response to the increasing demand for high-performance capacitors, with a simultaneous emphasis on minimizing their physical size, a common practice involves etching deep vias and coating them with functional layers to enhance operational efficiency ...
Zhouyi Xiang   +5 more
doaj   +2 more sources

Development of GUI-Driven AI Deep Learning Platform for Predicting Warpage Behavior of Fan-Out Wafer-Level Packaging [PDF]

open access: yesMicromachines
This study presents an artificial intelligence (AI) prediction platform driven by deep learning technologies, designed specifically to address the challenges associated with predicting warpage behavior in fan-out wafer-level packaging (FOWLP ...
Ching-Feng Yu   +4 more
doaj   +2 more sources

Multi-Grid Capacitive Transducers for Measuring the Surface Profile of Silicon Wafers [PDF]

open access: yesMicromachines, 2022
The measurements of wafers’ surface profile are crucial for safeguarding the fabrication quality of integrated circuits and MEMS devices. The current techniques measure the profile mainly by moving a capacitive or optical spacing sensing probe along ...
Panpan Zheng   +5 more
doaj   +2 more sources

A Comprehensive Experimental and Finite Element Analysis Study on the Bonding Strength Evaluation of Wafer-to-Wafer Hybrid Bonding with Polyimide Film Dielectrics [PDF]

open access: yesMicromachines
Polymer insulation layers such as polyimide (PI) have gradually replaced inorganic dielectric layers (SiO2, SiCN) in the integrated packaging process of hybrid bonding (HB).
Cong Mei   +10 more
doaj   +2 more sources

Mechanically Exfoliated InP Thin Films for Solar Energy Conversion Devices. [PDF]

open access: yesSmall Sci
This manuscript presents a significant demonstration in the field III‐V semiconductor solar energy conversion devices, focusing the potential of thin film III‐V semiconductors in conjugation with heterojunction solar cell architecture in addressing the cost‐related challenges.
Gupta B   +9 more
europepmc   +2 more sources

A CMOS-Compatible Process for ≥3 kV GaN Power HEMTs on 6-inch Sapphire Using In Situ SiN as the Gate Dielectric [PDF]

open access: yesMicromachines
The application of GaN HEMTs on silicon substrates in high-voltage environments is significantly limited due to their complex buffer layer structure and the difficulty in controlling wafer warpage. In this work, we successfully fabricated GaN power HEMTs
Jie Zhang   +8 more
doaj   +2 more sources

Emerging Copper-to-Copper Bonding Techniques: Enabling High-Density Interconnects for Heterogeneous Integration [PDF]

open access: yesNanomaterials
As CMOS technology continues to downsize to the nanometer range, the exponential growth predicted by Moore’s Law has been significantly decelerated. Doubling chip density in the two-dimensional domain will no longer be feasible without further device ...
Wenhan Bao   +4 more
doaj   +2 more sources

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