Results 101 to 110 of about 341 (156)
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Wafer-to-Wafer Bonding Fabrication Process-Induced Wafer Warpage
IEEE Transactions on Semiconductor Manufacturing, 2023Wei Feng +2 more
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Wafer warpage analysis of stacked wafers for 3D integration
Microelectronic Engineering, 2012The demand for wafer stacking technology has been increasing significantly. Although many technical challenges of wafer stacking have improved greatly, there are still many processing issues to be resolved. One of them is wafer warpage since it causes process and product failures such as delamination, cracking, mechanical stresses, and even electrical ...
Sarah Eunkyung Kim
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Effects of Wafer Warpage on the Misalignment in Wafer Level Stacking Process [PDF]
Journal of the Microelectronics and Packaging Society, 2013 본 연구에서는 웨이퍼 레벨 적층 과정에서 발생하는 웨이퍼 오정렬(misalignment) 현상과 웨이퍼 휘어짐(warpage)과의 관계에 대해서 조사하였다. 0.5µm 두께의 구리 박막 증착을 통해 최대 45µm의 휨 크기(bow height)를갖는 웨이퍼를 제작하였으며, 이 휘어진 웨이퍼와 일반 웨이퍼를 본딩하였을 때 6~15µm 정도의 정렬 오차가 발생하였다. 이는 약 5µm의 웨이퍼 확장(expansion)과 약 10µm의 미끄러짐(slip)의 복합 거동으로 설명할 수 있으며, 웨이퍼 휘어짐의 경우 확장 오정렬보다 본딩 과정에서의 미끄러짐 오정렬에 주로 기여하는 것으로 보인다.Abstract: In this study ...
Sarah Eunkyung Kim
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Effect of TEOS layer on wafer warpage for wafer-to-wafer bonding
Microelectronics ReliabilityHaruo Shimamoto, Katsuya Kikuchi
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Conference Proceedings. 1997 International Conference on Indium Phosphide and Related Materials, 2002
InP wafer warpage induced during its processing has been investigated. Magnitude and shape of wafer warpage caused by surface damage, which is presumed to give tensile stress to wafer, was influenced by its dopant. After MOCVD growth some wafer warpage changed but only a little and smooth surfaces of epi-layer were achieved.
T. Fukui, H. Kurita, N. Makino
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InP wafer warpage induced during its processing has been investigated. Magnitude and shape of wafer warpage caused by surface damage, which is presumed to give tensile stress to wafer, was influenced by its dopant. After MOCVD growth some wafer warpage changed but only a little and smooth surfaces of epi-layer were achieved.
T. Fukui, H. Kurita, N. Makino
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Journal of The Electrochemical Society, 1980
High temperature processing of Czochralski grown silicon wafers can create temperature gradients high enough to generate slip. The generation of slip and the slip patterns have been found to depend on three factors: the temperature and the temperature gradient, the amount and form of the precipitated oxygen, and the direction of the initial bow and the
B. Leroy, C. Plougonven
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High temperature processing of Czochralski grown silicon wafers can create temperature gradients high enough to generate slip. The generation of slip and the slip patterns have been found to depend on three factors: the temperature and the temperature gradient, the amount and form of the precipitated oxygen, and the direction of the initial bow and the
B. Leroy, C. Plougonven
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(Invited) Wafer Bow and Warpage
Japanese Journal of Applied Physics, 1981Initial Si wafer bow origin, and the relation between initial wafer bow and heat cycled wafer warpage were studied systematically through looking at crystal growth, from wafering process to heat cycle conditions. Initial bow and heat cycled warpages were studied from the view point of their sign and type, and their state was characterized as being ...
Shin'Ichiro Takasu +3 more
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Warpage Analysis of Underfilled Wafers
Journal of Electronic Packaging, 2004Wafer-level packaging (WLP) is one of the future trends in electronic packaging. Since 1994, many companies have released various WLP licenses. One of the common concerns of WLP is wafer warpage. Warpage of wafers tends to introduce cracking or delamination during dicing and low temperature storage processes.
Hai Ding, I. Charles Ume, Cheng Zhang
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Study of thinned Si wafer warpage in 3D stacked wafers
Microelectronics Reliability, 2010Abstract 3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer
Youngrae Kim +2 more
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Wafer Compression Molding Warpage Optimization for Wafer Level Package
2020 21st International Conference on Electronic Packaging Technology (ICEPT), 2020Because of low cost and small form factor, wafer level package is becoming more and more important in the development of technology research and productions. In this paper, wafer compression molding process is the main study content, including warpage control and its optimization.
Cheng Xu, Peng Sun, Zhu Liu, Jun Liu
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